Recover frame synchronization from a QPSK system impaired by a variable timing error.
The Variable Fractional Delay block introduces a varying timing error to a root raised cosine (RRC) filtered QPSK signal. After the AWGN block, the receive path is duplicated to compare performance with and without a Symbol Synchronizer block in the path. The Symbol Synchronizer block corrects for clock skew between the transmitter and receiver, aligning the output signal with a valid clock reference. For the timing error conditions in this example, the symbol synchronizer returns a vector containing 99, 100, or 101 symbols for a 200-sample input vector.
To align the bit stream along correct frame boundaries and determine valid frame indicators in the demodulated bit stream, the Frame Synchronizer block uses the start of packet index detected by the Preamble Detector block. The BER Data Decoding subsystem calculates the bit error rate (BER). The BER Data Decoding subsystem regenerate the input data bits rather than using the Bit Generation block output to avoid calculating the BER on nonvalid frames.
With a 20 dB signal-to-noise ratio and a variable timing error in the range of [0, 0.9] samples, signal recovery is successful on the receiver path that includes symbol synchronization. The timing error varies over time causing the constellation to oscillate between corrupted and clean states. The Before SymSync constellation diagram shows the effects of the variable timing error. The After Sym Sync constellation diagram shows that the symbol synchronizer removes the variable timing error signal impairment.
The BER with and without symbol synchronization show the performance improvement due to the Symbol Synchronizer block.
Error rate with symbol synchronization: 0.000 Error rate without symbol synchronization: 0.256