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Deep Learning Processor Register Map

During custom processor generation, AXI4 slave registers are created to enable MATLAB® or other master devices to control and program the deep learning (DL) processor IP core.

The DL processor IP core is generated by using the HDL Coder™ IP core generation workflow. The generated IP core contains a standard set of registers. For more information, see Custom IP Core Generation (HDL Coder).

For the full list of register offsets, see the Register Address Mapping table in the generated deep learning (DL) processor IP core report.

The image contains all the AXI4 registers created during IP core generation.

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