Custom Board and Reference Design
HDL Coder™ can generate an IP core that you can deploy to the Xilinx Zynq Platform. You can integrate the generated IP core into the default system reference design or into your own custom reference design that you can register for the board.
Export Reference Design
|Define external IO interface for board object
|Define external port interface for board object
|Add and define internal IO interface between generated IP core and existing IP cores
|Add and define AXI4 Master interface
|Add and define AXI4 slave interface
|Add AXI4-Stream interface (Since R2020a)
|Add AXI4-Stream Video interface (Since R2020a)
|Add clock and reset interface
Board and Reference Design
|Specify Xilinx EDK MHS project file
|Specify Xilinx Vivado exported block design Tcl file
|Include IP modules from your IP repository folder in your custom reference design
|Add and define custom parameters for your reference design
|Check property values in reference design object
|Check property values in board object
|Function handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
|Specify whether to use an Embedded Coder support package
|Function handle for callback function that gets executed after Build FPGA Bitstream task in the HDL Workflow Advisor
|Function handle for callback function that gets executed after Create Project task in the HDL Workflow Advisor
|Function handle for custom callback function that gets executed after Generate Software Interface task in the HDL Workflow Advisor
|Function handle for callback function that gets executed after Set Target Interface task in the HDL Workflow Advisor
|Function handle for callback function that gets executed after Set Target Reference Design task in the HDL Workflow Advisor
- Board and Reference Design Registration System
System for defining and registering boards and reference designs.
- Register a Custom Board
Define the interface and attributes of a custom SoC board. After defining the board, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
- Register a Custom Reference Design
Define the interface and attributes of a custom SoC reference design. After defining and registering the reference design, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
- Define Custom Parameters and Callback Functions for Custom Reference Design
Learn how to define custom parameters and custom callback functions for your custom reference design.
- Define and Add IP Repository to Custom Reference Design
Learn how you can create an IP repository and add the IP modules in the repository to your custom reference design.
Troubleshoot hardware connection issues.