HDL Verifier

Test and verify Verilog and VHDL using HDL simulators and FPGA boards

HDL Verifier™ lets you test and verify Verilog® and VHDL® designs for FPGAs, ASICs, and SoCs. You can verify RTL against test benches running in MATLAB® or Simulink® using cosimulation with an HDL simulator. These same test benches can be used with FPGA and SoC development boards to verify HDL implementations in hardware.

HDL Verifier provides tools for debugging and testing FPGA implementations on Xilinx® and Intel® boards. You can use MATLAB to write to and read from memory-mapped registers for testing designs on hardware. You can insert probes into designs and set trigger conditions to upload internal signals into MATLAB for visualization and analysis.

HDL Verifier generates verification models for use in RTL test benches, including Universal Verification Methodology (UVM) test benches. These models run natively in simulators that support the SystemVerilog Direct Programming Interface (DPI).

Getting Started

Learn the basics of HDL Verifier

Verification with Cosimulation

Cosimulation between HDL simulators and MATLAB and Simulink

Verification with FPGA Hardware

Connect an FPGA board with MATLAB and Simulink for verification and debug of hardware designs

Verification with UVM and SystemVerilog Components

Generation of UVM or SystemVerilog DPI components

Integrate Verification with HDL Code Generation

Generate test benches to verify HDL code generated with HDL Coder™

Transaction Level Model Generation

Generation of SystemC TLM virtual prototypes

Supported Hardware

Use third-party hardware with the related support package software.