The HDL Verifier™ software consists of MATLAB® functions, a MATLAB System object™, and a library of Simulink® blocks, all of which establish communication links between the HDL simulator and MATLAB or Simulink.
HDL Verifier software streamlines FPGA and ASIC development by integrating tools available for the following processes:
Developing specifications for hardware design reference models
Implementing a hardware design in HDL based on a reference model
Verifying the design against the reference design
The following figure shows how the HDL simulator and MathWorks® products fit into this hardware design scenario.
As the figure shows, HDL Verifier software connects tools that traditionally have been used discretely to perform specific steps in the design process. By connecting these tools, the link simplifies verification by allowing you to cosimulate the implementation and original specification directly. This cosimulation results in significant time savings and the elimination of errors inherent to manual comparison and inspection.
In addition to the preceding design scenario, HDL Verifier software enables you to work with tools in the following ways:
Use MATLAB or Simulink to create test signals and software test benches for HDL code
Use MATLAB or Simulink to provide a behavioral model for an HDL simulation
Use MATLAB analysis and visualization capabilities for real-time insight into an HDL implementation
Use Simulink to translate legacy HDL descriptions into system-level views
You can cosimulate a module using SystemVerilog, SystemC or both with MATLAB or Simulink using the HDL Verifier software. Write simple wrappers around the SystemC and make sure that the SystemVerilog cosimulation connections are to ports or signals of data types supported by the link cosimulation interface.
More discussion on how cosimulation works can be found in the following sections:
When linked with MATLAB, the HDL simulator functions as the client, as the following figure shows.
In this scenario, a MATLAB server function waits for service requests that it receives from an HDL simulator session. After receiving a request, the server establishes a communication link and invokes a specified MATLAB function that computes data for, verifies, or visualizes the HDL module (coded in VHDL® or Verilog®) that is under simulation in the HDL simulator.
After the server is running, you can start and configure the HDL simulator or use with MATLAB with the supplied HDL Verifier function:
The following figure shows how a MATLAB test bench function wraps around and communicates with the HDL simulator during a test bench simulation session.
The following figure shows how a MATLAB component function is wrapped around by and communicates with the HDL simulator during a component simulation session.
When you begin a specific test bench or component session, you specify parameters that identify the following information:
The mode and, if applicable, TCP/IP data for connecting to a MATLAB server
The MATLAB function that is associated with and executes on behalf of the HDL instance
Timing specifications and other control data that specifies when the module's MATLAB function is to be called
When linked with Simulink, the HDL simulator functions as the server, as shown in the following figure.
In this case, the HDL simulator responds to simulation requests it receives from cosimulation blocks in a Simulink model. You begin a cosimulation session from Simulink. After a session is started, you can use Simulink and the HDL simulator to monitor simulation progress and results. For example, you might add signals to an HDL simulator Wave window to monitor simulation timing diagrams.
Using the Block Parameters dialog box for an HDL Cosimulation block, you can configure the following:
Block input and output ports that correspond to signals (including internal signals) of an HDL module. You can specify sample times and fixed-point data types for individual block output ports if desired.
Type of communication and communication settings used for exchanging data between the simulation tools.
Rising-edge or falling-edge clocks to apply to your module. You can individually specify the period of each clock.
Tcl commands to run before and after the simulation.
Verifier software equips the HDL simulator with
a set of customized functions. For ModelSim, when you use the
vsimulink, you execute
the HDL simulator with an instance of an HDL module for cosimulation
with Simulink. After the module is loaded, you can start the
cosimulation session from Simulink. Incisive users can perform
the same operations with the function
HDL Verifier software also includes a block for generating value change dump (VCD) files. You can use VCD files generated with this block to perform the following tasks:
View Simulink simulation waveforms in your HDL simulation environment
Compare results of multiple simulation runs, using the same or different simulation environments
Use as input to post-simulation analysis tools
HDL Verifier contains the Cosimulation Wizard feature, which uses existing HDL code to create a customized MATLAB function (test bench or component), MATLAB System object, or Simulink HDL Cosimulation block. For more information, see Prepare to Import HDL Code for Cosimulation.
The mode of communication that you use for a link between the HDL simulator and MATLAB or Simulink depends on whether your application runs in a local, single-system configuration or in a network configuration. If these products and MathWorks products can run locally on the same system and your application requires only one communication channel, you have the option of choosing between shared memory and TCP/IP socket communication. Shared memory communication provides optimal performance and is the default mode of communication.
TCP/IP socket mode is more versatile. You can use it for single-system and network configurations. This option offers the greatest scalability. For more on TCP/IP socket communication, see TCP/IP Socket Ports.
All HDL Verifier MATLAB functions and the HDL Cosimulation block offer the same language-transparent feature set for both Verilog and VHDL models.
HDL Verifier software also supports mixed-language HDL models (models with both Verilog and VHDL components), allowing you to cosimulate VHDL and Verilog signals simultaneously. Both MATLAB and Simulink software can access components in different languages at any level.
The HDL Verifier User Guide provides instruction for using the verification software with supported HDL simulators for the following workflows:
Simulating an HDL Component in a MATLAB Test Bench Environment
Replacing an HDL Component with a MATLAB Component Function
Simulating an HDL Component in a Simulink Test Bench Environment
Replacing an HDL Component with a Simulink Algorithm
Recording Simulink Signal State Transitions for Post-Processing
|Product Feature||Required Products||Recommended Products||Supported Platforms|
|MATLAB and HDL simulator cosimulation (function)||MATLAB||Fixed-Point Designer™, Signal Processing Toolbox™||Windows® 32- and 64-bit; Linux® 64-bit|
|MATLAB and HDL simulator cosimulation (System object)||MATLAB and Fixed-Point Designer||Communications Toolbox™, DSP System Toolbox™||Windows 32- and 64-bit; Linux 64-bit|
|Simulink and HDL simulator cosimulation||Simulink, Fixed-Point Designer||Signal Processing Toolbox, DSP System Toolbox||Windows 32- and 64-bit; Linux 64-bit|