Use Variable-Sized Vector in SystemVerilog DPI Component

This example shows how to configure, generate, and use a SystemVerilog DPI (SVDPI) component with variable-length inputs or outputs.

Design Task

When you generate a SVDPI from a MATLAB® function that includes a variable-sized vector input or output, the result is a SystemVerilog module with a variable-sized input or output. Follow this example to configure, generate, and use the component in a SystemVerilog environment.

MATLAB Function

This example uses the function varSizeVectorSupport, a sinus function where the size of the input vec is variable. The output of the function is derived from the input, and therefore the output size is also variable.

Testbench

Use the provided varSizeVectorSupport_tb testbench to stimulate the function with fixed-sized signals. Then, generate a SystemVerilog testbench to test the generated SystemVerilog module. You can later change the port types of the generated SystemVerilog testbench (or write a new testbench) without the need to regenerate a DPI module from the varSizeVectorSupport function.

Configure Generation Options

To specify a supported toolchain, use a coder.config (MATLAB Coder) configuration object. Set the build_type to 'dll'.

configObj = coder.config('dll');

Then, set the toolchain to a supported simulator. Double-click the generated object in the MATLAB workspace to open the configuration object dialog box. Select Hardware on the left pane, and then under Build Process set Toolchain to a supported simulator (Cadence® Xcelium™, Siemens® Questa™ or ModelSim™).

Alternatively, you can set the toolchain at the MATLAB command prompt. For example, this code sets the toolchain to Siemens Questa/ModelSim (64-bit Windows).

configObj.Toolchain = 'Siemens Questa/ModelSim (64-bit Windows)';

Generate SystemVerilog DPI Component

To generate the SystemVerilog module, use the dpigen function.

• You must pass the configuration object to the dpigen function using the -config argument.

• Use the -args argument to specify the size of the generated ports. To set an upper bound value to the variable-length vector, specify that value in the coder.Type object. For example, to set an upper bound of 20 for vec, enter this code at the MATLAB command prompt.

dpigen varSizeVectorSupport -args {coder.typeof(1,[1 20],[0 1]),1,1} -config configObj

• Use inf to specify that the port size is of variable-length and unbounded in the generated SystemVerilog.

• To generate a SystemVerilog testbench from a MATLAB testbench function, use the -testbench argument.

dpigen varSizeVectorSupport -testbench varSizeVectorSupport_tb ...
    -args {coder.typeof(1,[1 inf],[0 1]),1,1} -config configObj

Generated Interface

Because vec is specified as a variable-sized vector during code generation in this example, the generated SystemVerilog includes the variable-sized input vec and output y. The data type for output y is derived from the input data type. These variable-sized ports are declared as a SystemVerilog open array ([ ]). This code shows the generated interface for the varSizeVectorSupport function.

module varSizeVectorSupport_dpi(
    input bit clk,
    input bit clk_enable,
    input bit reset,
    input real vec [],
    input real amp,
    input real freq,
    output shortint y []
);

Simulate in ModelSim

Verify that ModelSim is on the system path. Navigate to the directory named codegen\dll\varSizeVectorSupport\dpi_tb. To run the testbench and verify the generated component in ModelSim, enter this command at the MATLAB command prompt.

!vsim < run_tb_mq.do

Limitations

This feature does not support:

• Variable-sized matrices on the interface. If you have a matrix in your model, convert it to a variable-sized vector before connecting to an input or output.

• Structure data-types with fields of variable size

• Variable-sized arrays of structures

• Cross-platform DPI component generation

• Not supported on Synopsys® VCS® simulator