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FOC of PMSM Using FPGA-Based Motor Control Development Kit

This example shows how to use a Field-Oriented Control (FOC) algorithm for a Permanent Magnet Synchronous Motor (PMSM) by using blocks from the Motor Control Blockset™ on an FPGA device (Trenz Electronic™ Motor Control Development Kit TE0820).

The example lets you test the control algorithm by using a closed-loop system simulation. You can then generate HDL code for the control algorithm. The example includes a MATLAB® project that provides the models and the reference design. Use the project with the HDL Workflow Advisor for bit stream generation and for running an external mode model to interact with the processor.

You can apply the techniques shown in this example to partition and deploy the controller algorithms. This image shows the generalized workflow from model simulation to deployment of the controller algorithm onto an embedded hardware board.

Simulate a system test bench to gain insight into the behavior of the controller algorithm design. Then explore the design to see how the algorithm is partitioned. The high rate portion of the algorithm is partitioned into a model that is configured for HDL code generation. The low rate portion of the algorithm is partitioned into a model that is configured for C code generation. Generate C and HDL code from these models and learn how you can integrate this code into your design.

After exploring C and HDL code (model) for the algorithm, use automated deployment of code into the reference frameworks for the processor and programmable logic. Then, execute a test on the deployed application, log the results, and compare them with the simulation results.

Because this example deploys a bitstream and ARM® executable to a Xilinx® Zynq® hardware, you must set up the Xilinx Zynq hardware board before starting the example. To ensure that you have setup the environment correctly, follow and complete the Getting Started with Targeting Xilinx Zynq Platform (HDL Coder) example using your hardware configuration before starting this example. The figure shows the Hardware Board selection used in this demo.

Required Products

To run this example, these products are required:

  • MATLAB®

  • Simulink®

  • Embedded Coder®

  • Embedded Coder Support Package for Xilinx Zynq Platform

  • HDL Coder™

  • HDL Coder Support Package for Xilinx Zynq Platform

  • Motor Control Blockset

Required Hardware

Create Working Copy of MATLAB Project

To begin, create a working copy of the MATLAB project.

1. Use the following command to run the mcb_foc_fpga_demo_start script and create the MATLAB project:

mcb_foc_fpga_demo_start

The +task folder in the project has the scripts to automate different activities. The following image shows the summary of activities and dependencies listed inside a MATLAB project. For more information about MATLAB projects, see What Are Projects?

Simulate Algorithm Behavior

You can use the project shortcuts to open the Simulink models and simulate the algorithm behavior.

1. Select Project Shortcuts to view the available project shortcuts.

2. You can right-click the shortcuts to edit, open, and configure them.

3. Click the t1_openSimulationTestBenchModel project shortcut or use the following MATLAB command to open the model focZynqTestBench.

task.t1_openSimulationTestBenchModel

The Motor_And_Load subsystem consists of a mathematical model of a surface PMSM, motor load, encoder, and current sensor. The Controller_Algorithm subsystem includes an algorithm for I/O engineering unit conversion, an electrical position calculation algorithm, a rotor velocity calculation algorithm, a mode scheduler, and four control modes (disabled, open loop velocity control, encoder calibration, and closed loop velocity control). The C/D and D/C subsystems convert the data from continuous-time, variable time step solver and floating-point data type, to discrete-time, fixed time step solver and fixed-point data type, and vice-versa during simulation.

4. On the Simulation tab of the Simulink Toolstrip, click Run to simulate the model.

5. When the model finishes running, navigate to Simulation tab and click Data Inspector to open the Simulation Data Inspector.

6. In the Simulation Data Inspector, select the commandType, SpeedRef, SpeedFb, and controllerMode signals.

For the first two seconds, the controller calibrates the encoder position sensor. The encoder position sensor must be calibrated before the controller can achieve closed loop control. When position calibration begins, the motor accelerates using open loop control in order to identify the index pulse of the encoder.

After finding the index pulse, the controller commands and holds a zero position until the encoder offset is identified. During this period the motor speed is zero. After about two seconds, the controller begins closed-loop control and follows the given speed profile. During the closed-loop speed control, the FOC algorithm regulates the phase currents in the PMSM.

Partition Algorithm and Generate Code

You can partition the controller algorithm into sections that separately generate C code (for the designed software) and HDL code (for the designed hardware). See the reports created during the code generation step to determine ways to integrate the generated code and build your application according to your own embedded design.

1. In the focZynqTestBench model, open the Controller_Algorithm subsystem. The controller algorithm contains the Algorithm_C and Algorithm_HDL blocks, which reference the focZynqC and focZynqHDL models, respectively. The focZynqC model contains the portion of the algorithm to be implemented in software. Similarly, the focZynqHDL model contains the portion of the algorithm to be implemented on the FPGA hardware.

The parameters for the model are stored in the data dictionary. To access and modify the parameters, select Modeling > Model Explorer > focZynqTestBench > ExternalData.

2. Click the t2_generateCCode project shortcut or use the following MATLAB command to open the model focZynqC, generate C code, and generate a report.

task.t2_generateCCode

The focZynqC model contains the mode scheduler, velocity control loop, open-loop velocity controller, and a routine to automatically calibrate the encoder offset.

3. The Code Generation Report shows how the generated code corresponds to the model. If you are new to the Code Generation report, you can start with the Code Interface Report to view the function interface of the code. The C code is portable and can be integrated with any floating-point embedded processor that uses an ANSI-C compiler. For more information on the Code Generation Report, see Reports for Code Generation (Simulink Coder).

4. Click the t3_generateHdlCode project shortcut or use the following MATLAB command to open the model focZynqHdl, generate HDL code, and generate a report.

task.t3_generateHdlCode

The focZynqHdl model contains the algorithm for electrical position calculation and rotor velocity calculation, over-current checks, and the field-oriented controller algorithm.

5. The Code Generation Report shows how the HDL code corresponds to the model. If you are new to the Code Generation report, you can start by exploring the Generated Source Files pane of the report and selecting the focZynqHdl.vhd file that contains the entity specification. The HDL code for the algorithm is portable and can integrate with any FPGA that supports VHDL code.

Setup Xilinx Zynq Platform and Motor Boards

Use this procedure to connect and setup the hardware required for this example.

1. Setup the Xilinx Zynq hardware platform. For information about hardware setup, see . Install both Embedded Coder Support Package for Xilinx Zynq Platform and HDL Coder Support Package for Xilinx Zynq Platform.

2. Connect the Trenz Electronic Motor Control Development Kit TE0820 as shown below:

The preceding image shows these components:

          1. 5 V DC Power Supply

          2. SD - Card

          3. Micro USB cable for UART and JTAG

          4. Ethernet cable

          5. Encoder connector

          6. 24 V DC Power Supply

          7. Motor Power cable (A, B, C)

          8. 24 V Brushless DC Motor

          9. Switch 1 (S1) controls power to the driver board

3. Ensure that jumper J4 on the carrier module is set to SD and J3 on the motor driver card is set up for a single ended encoder.

4. Insert the encoder cable according to the picture below. For more information on the jumper settings, visit the Trenz Electronic website.

5. Download the Trenz TE0820 Linux Image, extract the ZIP archive, and copy the contents to the microSD card. Insert the microSD card in the J8 connector.

6. After you program the FPGA bitstream, press the S1 switch located on the motor driver card once to connect the 24V power supply to the MOSFETS. In case of any unexpected behavior from the device, use the S1 switch to disconnect the power.

Deploy Bitstream to Programmable Logic

To use the HDL Workflow Advisor to generate HDL code for the algorithm, follow these steps to package HDL into an IP core, integrate the IP core into a Xilinx reference design, and then create a bitstream:

1. Click the t4_openHdlWorkflowAdvisor project shortcut or use the following MATLAB command to open the HDL Workflow Advisor.

task.t4_openHdlWorkflowAdvisor

2. In the HDL Workflow Advisor > 1. Set Target > 1.1 Set Target Device and Synthesis Tool group, set the Target platform to Trenz TE0820 with CR00140. Trenz TE0820 with CR00140 is a Vivado® reference design containing the ADC, encoder, and PWM components. For information about creating this reference design, see Define Custom Board and Reference Design for Zynq Workflow (HDL Coder).

3. Select 1.3. Set Target Interface to identify the ports. The Target Platform Interfaces column entries that have the prefix "IP" indicate the connections that are registered with the Trenz motor control reference design.

4. Select 4.3 Build FPGA Bitstream > Run to Selected Task or click the t5_generateBitstreamAndInterfaceBlock project shortcut to generate the HDL code for the algorithm and create the FPGA bitstream from the Xilinx reference design. Alternatively, you can use the following MATLAB command to perform this action:

task.t5_generateBitstreamAndInterfaceBlock

5. Follow the progress of the bitstream generation on the new DOS command prompt that opens. In addition to generating the bitstream, the customized target generates the focZynqHdlAxiInterfaceLib software interface library. The library contains an AXI_Interface block. The AXI_Interface block, which contains the AXI4-Lite interface components, provides connectivity from the model deployed on the ARM processor to the model deployed on the programmable logic.

6. Run task 4.4 Program Target Device or click the t6_downloadBitstream project shortcut to program the FPGA. Alternatively, you can use the following MATLAB command to perform this action:

task.t6_downloadBitstream

Deploy Executable to ARM Processor

You can generate the C code for the controller and automatically integrate this code with a Linux® reference framework to build, deploy, and run the model as an executable on the ARM processor. You can then compare the data logged by the model running on the processor with the simulation results.

1. Click the t7_openZynqArmModel project shortcut to open the focZynqArmDeployment model. Alternatively, you can use the following MATLAB command to perform this action:

task.t7_openZynqArmModel

The focZynqArmDeployment model can generate C code, automatically integrate this code with a Linux ARM reference framework, and deploy the executable to the ARM processor on the Xilinx Zynq platform. The deployable model uses references to the original controller model and contains test stimulus, scope, and AXI_Interface library block that you created in the section Deploy Bitstream to Programmable Logic.

On the Hardware tab, click Monitor & Tune to build, deploy, and run the model as an executable on the ARM processor. The system compiles the generated code against the reference framework to create an executable. During model execution, Simulink monitors the signals and shows them in the scope.

          Press the S1 switch located on the Motor Driver card once. This connects the 24V power supply to the MOSFETS, after which the motor should run for 8 seconds. If you see any unexpected behavior in the device, use the S1 switch to disconnect the power.

3. Open the simulation data inspector to view the logged signals and compare them with the signals logged previously from the focZynqTestBench model. You can open simulation data inspector by clicking Data Inspector on the Simulation tab.

4. In the simulation data inspector, select the rotorVelocity signal.

During the encoder calibration mode, the compared signals initially differ and then match afterwards. This is because the simulated and real motors started with different rotor positions.

In contrast, the closed loop velocity control signals are very similar during simulation and hardware run. The small differences occur because the simulation model of the motor and sensors use data sheet values and do not explicitly account for the manufacturing tolerances of the physical motor.

More to Try in This Example

Variations to the example workflow that you can further try include:

  • Continue to explore the files included in this example to gain more insights into how the simulation, code generation, and automated deployment steps can help you develop a controller for your hardware.

  • HDL Coder supports floating-point single precision datatype. In the floating-point variant of the foczynqhdl model, you can utilize the ability of HDL Coder to generate HDL code from a model containing a mix of fixed-point and floating-point data types. Follow the same tasks in the example to implement the control algorithm with single-precision current control on a Xilinx Zynq SoC platform. To open the floating-point variant, right-click focZynqHdl/FOC_Velocity_Encoder/FOC_Current_Control and select Label Mode Active Choice > FloatingPoint within the Variant option.

See Also