Generate thyristor 6-pulse waveform in single-pulsing mode
Simscape / Electrical / Control / Pulse Width Modulation
The Thyristor 6-Pulse Generator block implements a thyristor 6-pulse waveform generator in single-pulsing mode.
You can use this block to perform phase-controlled AC-to-DC conversion by:
Measuring the synchronization angle of the AC signal with a phase-locked loop
Controlling a thyristor converter network with the pulses generated by this block
The figure shows the equivalent circuit for the Thyristor 6-Pulse Generator.
Based on the synchronization angle, theta, and the firing angle, alpha, the block internally generates six ramps, one for each of the pulse elements in its output vector.
The block generates a pulse at one of the outputs when the associated ramp meets or crosses the specified firing angle in the upward direction. This figure shows such a pulse generation mechanism for one of the outputs.
Set the pulse ordering strategy to modify the distinct phase-shift of each ramp, and as a result, the order of generated pulses:
Pulse ordering property to
Sequential device order to generate
pulses in sequential order. Use this strategy to generate pulses for the
(Three-Phase) block or other thyristor networks that
use sequential ordering.
Pulse ordering property to
Natural order of commutation to generate
pulses in the natural order. Use this strategy to generate pulses for
thyristor networks that use natural ordering.
theta— Synchronization angle, radians
Synchronization angle in the range
[0, 2*pi], in
alpha— Firing angle, radians
Thyristor firing angle in radians.
P— Pulse vector
Thyristor pulse vector.
Pulse ordering— Pulse ordering strategy
Sequential device order(default) |
Natural order of commutation
Specify the rule for pulse ordering based on the configuration of the
thyristor network you are controlling. Use the
device order strategy to generate pulses for the
Pulse width (rad)— Pulse width
5*pi/6 rad(default) | positive scalar in range [0, pi]
Specify the width of each pulse in the range
Sample time (-1 for inherited)— Block sample time
1e-5(default) | positive scalar
Time, in s, between consecutive block executions. During execution, the block produces outputs and, if appropriate, updates its internal state. For more information, see What Is Sample Time? and Specify Sample Time.
If this block is inside a triggered subsystem, inherit the
sample time by setting this parameter to
-1. If this block is in a
continuous variable-step model, specify the sample time explicitly using a positive
 Pelly, B. R. Thyristor Phase-Controlled Converters and Cycloconverters: Operation, Control, and Performance. New York, NY: John Wiley & Sons, Inc., 1971.