SIO RLDRAM II Architectural Kit
This example shows how to implement a separate I/O (SIO) RLDRAM II interface for pre-layout analysis or post-layout verification.
This SIO RLDRAM II architectural signal integrity kit includes all transfer nets, timing models, waveform processing levels and generic models for an SIO RLDRAM II interface. This includes generic buffer models for the controller and RLDRAM along with fully functional timing models and complete waveform processing levels. You can modify the kit to match your exact implementation. Then, perform complete pre-layout solution space analysis and/or full post-layout verification for waveform quality and timing margins.
Open SIO RLDRAM II Kit
Open the SIO RLDRAM II kit in the Parallel Link Designer app using the
For more information about the SIO RLDRAM II architectural signal integrity kit, including block diagrams, system configurations, transfer nets and libraries, along with instructions on how to customize the kit for a specific implementation, refer to the document RLDRAM2_SIO.pdf that is attached to this example as a supporting file.