The Simulink® Design Verifier™ software can generate test cases that satisfy coverage objectives for your model, including:
Test cases help you confirm model performance by demonstrating how the blocks in the model execute in different modes. When generating test cases, the software performs a formal analysis of your model. After completing the analysis, the software provides several ways for you to review the results.
If your model does not have conditions, decisions, or custom test objectives, then Simulink Design Verifier generates a test case that represents a basic simulation of your model. The test inputs satisfy minimum or maximum constraints on input ports and intermediate signal values satisfy constraints specified by the Test Condition blocks in the model.
For customizing test cases for your Simulink models, Simulink Design Verifier provides two blocks:
To customize test cases for a Simulink model or Stateflow® chart, Simulink Design Verifier provides two MATLAB® functions. You can use these functions in a MATLAB Function block. Both functions are active in generated code and in Simulink Design Verifier.
Identify mathematical relationships for testing in a form that can be more natural than using block parameters.
Support specifying multiple objectives, assumptions, or conditions without complicating the model.
Provide access to the power of MATLAB.
Support separation of verification and model design.
Simulink Design Verifier blocks and functions are saved with a model. If you open the model on a MATLAB installation that does not have a Simulink Design Verifier license, you can see the blocks and functions, but they do not produce results.