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AXI4-Register IIO Read (HOST)

Read memory-mapped registers into simulation model

Since R2020b

Add-On Required: This feature requires the SoC Blockset Support Package for Xilinx Devices add-on.

  • AXI4-Register IIO Read icon

SoC Blockset Support Package for Xilinx Devices / Common / Host I/O


The AXI4-Register IIO Read (HOST) block reads value from memory-mapped registers in the programmable logic of the connected Xilinx® SoC device to a running Simulink® model on the host computer. This block enables low-latency high-throughput data transmission between your simulation model and the FPGA registers on the SoC device.

The AXI4-Register IIO Read (HOST) block receives a copy of the memory-mapped registers from the programmable logic in the SoC device on the host computer. This block uses the Industrial I/O (IIO) library driver to create a network server daemon on the SoC device and client host computer to pass the register data copies to the host computer running the simulated portion of the model. This diagram shows the connection between the memory-mapped registers, central interconnect, and communication bridge to the running Simulink model.

AXI4-Register IIO Read (HOST) diagram



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This block outputs the N-by-1 vector read from memory-mapped registers on the IP core, starting from the Register offset.

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean


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Enter the path and name of the IP core.


If you use HDL Coder™ to generate the IP core, HDL Coder maps the IP core to mwipcore0:mmrd0.

Enter the offset of the register from the base address of the IP core on the device. The block reads data from this register. Use the hex2dec function when you specify the address offset using a hexadecimal number character vector.


If you use HDL Coder to generate the IP core, you can get the value of the address offset from the “Register Address Mapping” section of Custom IP Core Report (HDL Coder). For more information, see Register Address Mapping (HDL Coder).

Enter the network address of the connected SoC device.


Specify the maximum time out delay for the register read.

Select the data type used by the IP core on the device.

The signal data output by the AXI4-Register IIO Read (HOST) block polls directly from the IP core using AXI4-Lite protocol. The Sample time parameter value or the base-rate of the subsystem specifies the polling rate of the registers.

When connected to a board, this block writes data directly to the board. When used in a simulation environment, clear this parameter to enable simulation without error due to lack of IIO connection. When cleared, the data displayed in the data output port does not reflect actual data.

Version History

Introduced in R2020b