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Transmit and Receive Tone Using Fixed Reference Design Workflow on RFSoC Device

This example shows how to design and implement a hardware algorithm, which transmits and receives a tone signal, on FPGA fabric by using the RFSoC Support for a fixed reference design workflow.

In this example, you generate HDL code for the algorithm as an IP core and integrate it in a reference design to build a system. Then, you deploy the system to hardware and visualize the received signal in Simulink®.

This example supports these hardware platforms:

  • Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit and XM500 balun card

  • Xilinx Zynq UltraScale+ RFSoC ZCU216 evaluation kit and XM655 balun card


Using the Support for Fixed Reference Design workflow, you can focus on the algorithm component and integrate it in a predefined reference design that defines the architecture. This workflow can be a good option for rapid prototyping when a reference design that meets your system requirements is available for deployment.

For modeling an algorithm with architecture, such as by using external memory and input/output (I/O) in Simulink, use the SoC Blockset™ product. For an example that shows how to model the algorithm and FPGA or SoC architecture and that shows the workflow to design and implement the complete SoC model, see Transmit and Receive Tone Using Xilinx RFSoC Device - Part 1 System Design.

This example contains four models. All of the models generate a sinusoid signal from the FPGA using the NCO HDL Optimized block and send the signal through the digital-to-analog converter (DAC) channels of the RFSoC device. Then the signal is received back from the analog-to-digital converter (ADC) channels in the FPGA. The receive-side FPGA logic involves selection of one of the received ADC channels and the logic to capture data in memory. Then the received data from memory is visualized in Simulink using the host I/O models. These four models differ slightly from one another.

  • soc_datacapture_8x8real_zcu111_top — Capture real data with eight channels in the internal BRAM FIFO.

  • soc_datacapture_4x4IQ_zcu111_top — Capture complex in-phase/quadrature (I/Q) data with four channels in the internal BRAM FIFO.

  • soc_datacapture_8x8IQMTS_zcu111_top — Capture complex I/Q Data with eight channels in the internal BRAM FIFO and multi-tile sync enabled for various channels.

  • soc_datacapture_4x4realDDR4_zcu111_top — Capture real data with four channels in the external DDR4 memory.

This example shows the workflow using the soc_datacapture_8x8real_zcu111_top model. The workflow steps are common for all of these models.


To work with the RFSoC support for a fixed reference design workflow, you must install and configure additional support packages and third-party tools. For more information, see Xilinx Devices.

Design Hardware Algorithm

To design the hardware algorithm, you must choose the reference design that meets your requirements by using the SoC Model Creator tool. To open this tool, enter this command at the MATLAB® command prompt.


To create the model, follow these steps in the SoC Model Creator tool.

  1. Select Reference design board as Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit.

  2. Select Reference design name as Real ADC/DAC Interface.

  3. Set Top Model Name to soc_datacapture_8x8real_zcu111.

  4. Select the model type as FPGA only.

  5. Set required reference design parameters in the Reference Design Parameters pane.

  6. Select required interfaces in the Internal Interfaces pane.

  7. Select required interfaces in the External IO Interfaces pane.

  8. Add required registers in the AXI Registers pane.

  9. Click Create.

The tool generates the soc_datacapture_8x8real_zcu111 top model and the soc_datacapture_8x8real_zcu111_fpga FPGA model. Subsystem in the FPGA model is preconfigured with ports to match your chosen reference design. You can add your algorithm inside the Transmit and Receive Tone subsystem and add stimuli and scopes in the top model for simulating your algorithm. The model soc_datacapture_8x8real_zcu111_fpga is the hardware generation model that adds the transmit and receive algorithm.




Simulate the model and observe the DAC1 spectrum plot in the DAC_Out_Tile0 testbench subsystem, the DAC2 spectrum plot in the DAC_Out_Tile1 testbench subsystem for the transmitted tone signal of 107.5 MHz, and the ADC captured scope plot for the selected ADC channel. Modify the numerically-controlled oscillator (NCO) tone frequency value by modifying the NCO Freq testbench block, and then observe the corresponding change in the tone signal on the spectrum analyzer.

Implement and Run on Hardware

Set the DUT subsystem of the FPGA model as an atomic subsystem by right-clicking the top-level DUT design subsystem Transmit and Receive Tone and selecting Block Parameters (Subsystem) and Treat as atomic unit. Next, set up the Vivado® tool version using this command (which assumes that Xilinx Vivado is installed at C:\Xilinx\Vivado\2020.2\bin).

hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','C:\Xilinx\Vivado\2020.2\bin\vivado.bat');

To implement the model on a supported SoC board, use the SoC Builder tool. Before using this tool, ensure that the Hardware Board is set to Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit on the System on Chip tab of the Simulink toolstrip.

To open SoC Builder, click Configure, Build, & Deploy. After the SoC Builder tool opens, follow these steps.

  1. On the Setup screen, select Build using fixed reference design. Click Next.

  2. On the Select Build Action screen, select Build, load, and run. Click Next.

  3. On the Select Project Folder screen, specify the project folder. Click Next.

  4. On the Review Hardware Mapping screen, view the memory map by clicking View/Edit. Click Next.

  5. On the Validate Model screen, check the compatibility of the model for implementation by clicking Validate. Click Next.

  6. On the Build Model screen, build the model by clicking Build. An external shell opens when FPGA synthesis begins. Click Next.

  7. On the Connect Hardware screen, test the connectivity of the host computer with the SoC board by clicking Test Connection. To go to the Load Bitstream screen, click Next.

The Build step integrates the newly generated IP core into the RFSoC IP core reference design, generates the corresponding embedded system with bitstream, and generates a host interface library and a host interface model.

Host Interface Model

Use the generated host interface model as a starting point for host targeting. Because the generated model is overwritten each time you build the system, saving this model with a unique name and developing your host model are recommended.

Load the bitstream onto the hardware by clicking Load on the Load Bitstream screen.

Hardware Setup for ZCU111 Board

To complete the loopback between the DACs and ADCs, connect the SMA connectors on the XM500 balun card, according to the connections provided in this table. Use DC blocks for the differential channels loopback.

Host Interface Model



To configure the hardware and get data, run the host model corresponding to your bitstream loaded on the hardware. Before running the host model, make sure that all of the host I/O blocks in the host model have the correct IP address. You can observe the ADC-captured spectrum output and scope output of the selected ADC channel.

8x8 Real Host Model Spectrum Output

8x8 Real Host Model Scope Output

Change the ADC_select register to capture a different ADC channel, and then run the host model. Change the NCO_Freq register to send a different tone to the DAC channels, and then observe the corresponding ADC-captured spectrum output after running the host model. You can change the scaling values of the DAC channels and observe the effects in the ADC-captured spectrum output.

Implement and Run Example Models on ZCU111 Board

To generate the IP core and run the models soc_datacapture_4x4IQ_zcu111_top, soc_datacapture_8x8IQMTS_zcu111_top, and soc_datacapture_4x4realDDR4_zcu111_top on the hardware, follow the SoC Builder steps in previous sections of this example.

To see the ADC-captured tone, run the corresponding host models.

The remaining host models are:

  • soc_datacapture_4x4IQ_hostio.slx

  • soc_datacapture_8x8IQMTS_hostio.slx

  • soc_datacapture_4x4realDDR4_hostio.slx

Implement and Run Example Models on ZCU216 Board

To generate the IP core and run the models soc_datacapture_8x8real_zcu216_top, soc_datacapture_4x4IQ_zcu216_top, soc_datacapture_8x8IQMTS_zcu216_top, and soc_datac,apture_4x4realDDR4_zcu216_top on the hardware, follow the SoC Builder steps in previous sections of this example and use the hardware setup as described in the next section for connections.

Hardware Setup for ZCU216 Board

To see the ADC-captured tone, run the corresponding host models.


Using the RFSoC support for a fixed reference design workflow, you implemented an algorithm that transmitted a tone signal and received it back into the FPGA on the RFSoC device. You verified that the system worked as expected on the hardware. You can use this example as a reference and prototype for your wireless algorithm on the Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit or Xilinx Zynq UltraScale+ RFSoC ZCU216 evaluation kit.

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