Capture raw data using FPGA input and output (IO) application programming interface (API) from the Xilinx® Zynq® UltraScale+™ ZCU111 evaluation kit or Xilinx Zynq UltraScale+ ZCU216 evaluation kit. Configure an SoC model for the HDL code generation by using the HDL Workflow Advisor. Generate the HDL code for your algorithm, build and deploy the HDL design on an RFSoC device, and run a MATLAB® script to interactively capture data from the deployed HDL design.
- Create RFSoC HDL Coder Models
This workflow customizes and designs an RFSoC model using the Zynq RFSoC Template Builder tool.
- ARM Targeting
Design and deploy algorithms to the ARM processor.
|Zynq RFSoC Template Builder||Generate template model based on selected RFSoC reference design|