Memory IIO Write
Write from simulation model to a shared memory region
SoC Blockset Support Package for Xilinx Devices / Host I/O
The Memory IIO Write block performs random-access write transactions to DDR memory in the connected Xilinx® SoC device from a Simulink® model running on the host computer. This block enables low-latency high-throughput data transmission between your simulation model and the DDR memory on the SoC device.
The Memory IIO Write block sends data to the DDR memory on the SoC device from the host computer. This block uses the Industrial I/O (IIO) library driver to create a network server daemon on the SoC device and client host computer to pass the data from the host computer running the simulated portion of the model. This diagram shows the connection between the FPGA, DDR memory, and communication bridge to the Simulink model.
data — Data to shared memory
scalar | vector
This port receives the data vector that it writes to the memory.
addr — Memory address offset for write requests
scalar | vector
The offset of the memory address from the base address of the IP core on the device. The block writes data to this address.
To enable this port, select Enable address offset port.
Device name — Name of IP core device
mwipcore0:sharedmem0:wr0 (default) | IP core name and channel
Enter the name and channel of the IP core on the FPGA as a colon-separated list.
If you are using HDL Coder™ to generate the IP core, HDL Coder maps the IP core to
mwipcore0 and uses channel
Enable address offset port — Enable address offset port
off (default) | on
Select this parameter to use the address offset from a port.
On — The Address offset parameter is disabled, and an addr input port is created.
Off — The Address offset parameter is enabled.
Address offset — Offset of memory address from base address of IP core
Enter the offset of the memory from the base address of the IP core on the device. The block reads data from this address.
If you use HDL Coder to generate the IP core, you can get the value of the address offset from the “Register Address Mapping” section of Custom IP Core Report (HDL Coder). For more information, see Register Address Mapping (HDL Coder).
To enable this parameter, clear the Enable address offset port parameter.
IP address — Network address of SoC device
192.168.1.101 (default) | network address
Enter the network address of the connected SoC device.
Timeout — Timeout for memory write
Inf (default) | positive scalar
Specify the maximum timeout delay for the memory write.
Enable simulation I/O — Read and write data from board
on (default) | off
When the host computer is connected to a board and this parameter is on, this block writes data directly to the board. When you use this parameter in a simulation environment, clear the parameter to enable simulation without error due to lack of IIO connection. When you clear this parameter, the data that the data output port displays does not reflect actual data.
To get a list of available IIO device names and channels, open a terminal to the
Zynq® device and execute this command:
iio_info. This display shows
the sample output from the
Introduced in R2023a