Code Verification and Validation with PIL on the ARM Cortex M3 Core of the F28M3x Concerto Processor

This example uses:

This example shows you how to use Texas Instruments C2000 F28M3x Concerto Processor for code verification and validation using PIL in C2000™ Microcontroller Blockset.

Introduction

In this example you will learn how to configure a Simulink® model to run Processor-In-the-Loop (PIL) simulations. In a PIL simulation, the generated code runs on the Texas Instruments C2000 Concerto Processor. The results of the PIL simulation are transferred to Simulink® to verify the numerical equivalence of the simulation and the code generation results. The PIL verification process is a crucial part of the development cycle to ensure that the behavior of the deployment code matches the design.

This example introduces the Simulink code generation and verification workflow by showing you how to:

Configure a Simulink® model to run Model Block PIL simulations on the Texas Instruments C2000 Concerto ARM Cortex M3 Core.
Configure a Simulink model to run Top-Model PIL simulations on the Texas Instruments C2000 Concerto ARM Cortex M3 Core.
Configure a Simulink model to run PIL Block simulations on the Texas Instruments C2000 Concerto ARM Cortex M3 Core.

To run PIL on the C28x Core of Concerto, please refer to the Code Verification and Validation with PIL

Prerequisites

This example runs on the ARM Cortex M3 CPU of the Concerto processor. We recommend completing the Getting Started with C2000 Microcontroller Blockset for F28M3x Concerto Processors.

Required Hardware

To run this example you will need the following hardware:

F28M36 Concerto Control Card or
F28M35 Concerto Control Card

The Texas Instruments ControlCARDs provide serial over USB capabilities. This allows serial communication from the target to your host computer over the USB connection to the board. The controlCARDs also provide Ethernet capabilities. We will use both Ethernet and serial connections in this example to exchange data from Simulink to the target.

Choose a Communication Interface for PIL Simulation

The Texas Instruments C2000 Concerto processor supports serial and Ethernet communication interface for PIL. The Serial Communication interface uses UART0 and the Ethernet communication interface uses Ethernet port 17725 for PIL.

For Serial PIL: You can access UART0 via the USB cable connected to the controlCARD through a virtual COM port. For more information on how to configure the Virtual COM port refer to this page. Note the COM port number of the USB Serial Port showing in your Windows Device Manager under Ports "(COM & LPT)"

1. Connect the USB cable from your host machine to the controlCARD:

Open your model configured for code generation on a Texas Instruments C2000 Concerto processor ARM Cortex M3 core. Browse to Configuration Parameters > Hardware Implementation > Target hardware resources > PIL > Serial Port and enter the COM port number corresponding to your controlCARD.

As an example, see the settings in the f28m35x_m3_pil_block model as shown below. For example, enter COM1 in the Serial port field

For TCP/IP PIL:

1. Connect the USB cable from your host machine to the controlCARD:

Open your model configured for code generation on a Texas Instruments C2000 Concerto processor ARM Cortex M3 core. By default this model is configured for Serial PIL over UART0. Go to Configuration Parameters > Hardware Implementation > Target Hardware Resources > PIL > PIL Communication Interface and change it to TCP/IP.

2. The default Ethernet configuration uses DHCP for Local IP Address Assignment. To configure for Static IP address assignment, In the Ethernet tab, uncheck the Enable DHCP for local IP address assignment and enter the desired Static IP Address and subnet mask.

Verify the Generated Code for a Subsystem Using a PIL Block

This example shows how to use a PIL block for subsystem code verification. With this approach:

You can verify the code generated for a subsystem
You must swap your original subsystem with a generated PIL block; make sure to avoid saving your model in this state as you would lose your original subsystem

1. Open the f28m35x_m3_pil_block model. This model is configured for the TI Concerto F28M35x (ARM Cortex-M3) target. To configure the model to run on TI Concerto F28M36x (ARM Cortex-M3) you can change the Hardware board in the Configuration Parameters > Hardware Implementation pane. The objective here is to create a PIL block out of the Controller subsystem that you will run on the Texas Instruments C2000 Concerto F28M35x processor ARM Cortex M3 core.

Note: If you choose to select a different TI C2000 processors other than default configured model, ensure you set the Total number of instances allowed per top model to Multiple under Configuration parameters > Model Referencing > Options for referencing this model.

2. Choose a PIL communication interface by following the steps in Task 1 above.

3. Create a PIL block for the Controller subsystem by following Task Example 1 of the Test Generated Code with SIL and PIL Simulations (Embedded Coder).

4. Run the PIL simulation by following Example 1 of the Test Generated Code with SIL and PIL Simulations (Embedded Coder).

5. You can switch between the original and PIL block subsystems by double clicking on the Manual Switch block. Double click on the Numerical Differences block to see the difference between the simulated Controller subsystem and the PIL block running on the Texas Instruments C2000 Concerto board.

Verify Referenced Model Code Using PIL

This example shows how to verify the generated code for a referenced model by running a PIL simulation. With this approach:

You can verify code generated for referenced models
You can easily switch a Model block between normal and PIL simulation mode

1. Open the f28m35x_m3_model_pil_block model. This model is configured for TI Concerto F28M35x (ARM Cortex-M3) target. To configure the model to run on TI Concerto F28M36x (ARM Cortex-M3) you can change the Hardware board in the Configuration Parameters > Hardware Implementation pane. The model contains two Model blocks that both point at the same referenced model. You will configure one of the Model blocks to run in PIL simulation mode and the other in normal mode.

2. Choose a PIL serial communication interface by following the steps in Task 1 above.

3. Configure and run CounterA Model block in PIL simulation mode by following Example 2 of the Test Generated Code with SIL and PIL Simulations (Embedded Coder).

4. When the model starts running, Scope1 displays the PIL simulation output running on the Texas Instruments C2000 Concerto processor ARM Cortex M3 core while Scope2 shows the normal mode simulation output.

Verify Top Model Code Using PIL

This example shows how to verify the generated code for a model by running a PIL simulation. With this approach:

You can verify code generated for a top model
You can easily switch the entire model between normal and PIL simulation mode

1. Open the f28m35x_m3_top_model_pil model. This model is configured for the TI Concerto F28M35x (ARM Cortex-M3) target. To configure the model to run on TI Concerto F28M36x (ARM Cortex-M3) target, you can change the target hardware in the Configuration Parameters > Hardware Implementation pane.

2. Choose a PIL serial communication interface by following the steps in Task 1 above.

3. Run the top model PIL simulation by following Example 3 of the Test Generated Code with SIL and PIL Simulations (Embedded Coder).

4. When the PIL simulation is completed, a logsOut variable is created in the base workspace. The logsOut data contains PIL simulation results. You can access the logged data for signals count_a and count_b using the following commands:

count_a = get(logsOut,'count_a');
count_a.Values.Data

count_b = get(logsOut,'count_b');
count_b.Values.Data