Unable to execute `ADC/DAC Loopback Data Capture' example of HDL Coder Support Package for Xilinx RFSoC Devices.

While trying to execute the `ADC/DAC Loopback Data Capture' example of HDL Coder Support Package for Xilinx RFSoC Devices I am facing an error in the HDL Workflow Advisor at Step 4.1. Create Project.

Tried this with Matlab r2021a and r2021b. Both are giving the same error.

Using Xilinx Vivado 2020.2.

Board: ZCU111

Is it because of version mismatch error, because as per the documentation the HDL Coder for RFSoC supports Vivado 2020.2 while the HDL Coder Support Page requires Vivado 2020.1 as the tested and suppported version. Moreover in the HDL Workflow Advisor, the Set Target Reference design describes the Reference design tool version as 2020.2 . I am confused.

I have attached the log file, any help is really appreciated.

Regards

[Luk McCregor]

Same problem here. Any solutions?

Answer 1

[Aunullah Qaiser]

The problem was with Xilinx Vivado installation. I had to re install v2020.2 with Addon for Matlab support and RFSoC board support enabled. That solved the issue.

[Luk McCregor]

Thanks @Aunullah Qaiser, i will try the same thing

Answer 2

[Praful Pai]

You can try the following:

1. Apply Patches for Existing / Known Bugs: This Particular Bug Report (#2656440) causes HDL IP core generation using Xilinx Vivado to fail as of January 1, 2022. Please ensure you are on Update 6 for R2021a or apply the patch from the above link.
2. Check if you have appropriate devices selected in the Xilinx Information Centre. You can open Xilinx Information Centre on the computer and got to Add Devices and check if the appropriate device is selected under Devices > SoCs > Zynq + RFSoC.
3. Finally, please check the Xilinx License Manager to see if there are any issues highlighted with the licenses. Any license issues might be highlighted in red.

Hope this is helpful. Thanks!