Generating Verilog for Butterworth IIR lowpass filter, incorrect simulation

Using fdatool, I have generated a lowpass filter with cutoff frequency of 200Hz and sampling frequency 48kHz. The order of the filter is specified and it is 10. The filter arithmetic is 16-bits fixed point. The filter is supposed to be used as a part of an equalizer. The generated model is behaving correctly in Simulink. However, generated Verilog code for FPGA prototyping does not simulate correctly. A simulation waveform with chirp stimuli is provided.

As you can see, the output is always less than 0, which it seems like incorrect behaviour. I have tried changing cutoff frequency, and various quantization parameters.

Moreover,I have tested bandpass filters with various configurations, and they all work properly. There is only a problem when I am generating lowpass and highpass filters. Is there any way to generate a correct HDL code for this filter? Please correct me if any of the steps I am doing are wrong.

Answer 1

[Kiran Kintali]

thank you for bringing this to our attention. please report the issue to technical support with reproduction steps for further investigation.

Answer 2

[Bharath Venkataraman]

Can you try running the HDL code and testbench in ModelSim to see if it passes? If it does, that means that HDL code matches the MATLAB filter behavior. If not, it would be good to see what filter you generated HDL code for, to enable further debugging.

[Dordije Boskovic]

Thank you for your answer. I have tried running it in ModelSim. That is where I have extracted the attached simulation waveform from. I have followed all the steps as I did for bandpass filters which worked, as I have already mentioned. However, lowpass filters do not work.