Dual Port Ram - Output Port Widths or Dimension Error

Hello everyone.

I have an issue with my port dimensions on the output of a Dual Port RAM. It the output of an internal block of a Simulink DDR main block, the signal is 'rd_dout'. The exact error is:

"Error in port widths or dimensions. Output port 1 of 'hdl_coder_ddr/DDR/Simple Dual Port RAM System' is a [1x1] matrix. Caused by: May be caused by unspecified input dimensions, which cause Simulink to assign default input port dimensions. This issue can happen when an input port is in a loop, is driven by a Ground block or a source with unspecified dimensions, or has unconnected signal lines. Consider adding a Signal Specification block with specified dimensions in front of the input port. Component:Simulink | Category:Model error Error in port widths or dimensions. Input port 1 of 'hdl_coder_ddr/DDR/Delay1' is a one dimensional vector with 1 elements."

I have confirmed that all the internal inputs/outputs to the internal DDR blocks are 'Inherit : auto' and all of the inputs/outputs on the top level are fixed. For some reason, I get a lot of '?' on my signals which is confusing as some of them are simple 'bool' types and a mismatch is unlikely. I believe that this error is due to the way that Simulink processes internal signals inbetween my specified input to output chain.

I hagve tried the following:

1. Manually set input/output data types
2. Place a signal specification block

Does anyone have any ideas, I have attatched some images for reference.

The output 'axi_rd_data', 'axi_rd_s2m' and 'axi_wr_s2m' connects directly into another subsystem in the top level, creating a loop.

Answer 1

[Bharath Venkataraman]

Please try putting a signal specification block before each of the RAM inputs. Make sure that each signal specification block has the entries for dimension, complexity and data type.

[Zeiss Precision]

That does not seem to fix the issue. There is still '?' on the inputs which indicates it cant inherit the previous data type even after its explicitly stated.

[Bharath Venkataraman]

Any chance you can share a part of, if not the entire model that shows the problem?