For HDL code generation, the float point to fixed point conversion is ok. Because of "Accounting for output port latency: 10 cycles", the test bench does not agree with the HDL code. How to solve this problem?
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jing xu
el 30 de Oct. de 2018
Comentada: Rumala Niyathi
el 24 de Nov. de 2018
For HDL code generation, the float point to fixed point conversion is ok. Because of "Accounting for output port latency: 10 cycles", the test bench does not agree with the HDL code. How to solve this problem?
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Bharath Venkataraman
el 31 de Oct. de 2018
The HDL testbench will account for this latency. So generating the HDL code and testbench will let you run the modified testbench with the appropriate latency of 10 cycles.
If you want to balance the delay added in one path to the other, turn Balance Delays option on and the parallel paths will get an additional latency of 10 cycles to match.
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Bharath Venkataraman
el 2 de Nov. de 2018
It appears that delay balancing cannot balance the delays added because the added delays are in a feedback loop. If you can share the code, I can get someone to look into it.
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