FPGA-in-the-Loop (FIL) Simulink Block Creation

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andrew kurtz
andrew kurtz el 9 de En. de 2019
Comentada: andrew kurtz el 10 de En. de 2019
Hello, I am having difficulty in creating a FIL block to perform median filtering on a data stream.
I have been using the "FILSimulinkWithVHTExample" example file and attempting to substitute the HDL Algorithm_fil1 block with one that is designated for my Xilinx FPGA. (See block with arrow pointing to it)
Question 1 - Copy.png
The FIL model, I'm assuming, looks something like this:
Question 2.PNG
Where input port 1 is of type 'single', and 2-6 are Boolean. Output 1 is boolean, while output 2 is a "pixeldata". However,when I try to generate HDL code, I get an error
Question 3 - Copy.PNG
Does anyone have any advice or examples on making a working FIL block that is capable of performing an image processing algorithm? I am unable to deconstruct the provided FIL block to determine what its intial structure was.
Thanks.

Respuestas (1)

Bharath Venkataraman
Bharath Venkataraman el 9 de En. de 2019
Does your HDL code handle single datatype pixel input? You may want to try it with the appropriate fixed-point pixel data that the HDL handles.
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Brian Ogilvie
Brian Ogilvie el 10 de En. de 2019
Hi Andrew,
It seems like you are trying to use FIL with a matrix input, which is not allowed. Recall that a matrix in Simulink can be a mathmatical matrix or more often in signal and video processing it can represent a collection of samples by channels. The FIL block outlaws this ambiguious input.
The FIL block does accept vectors of samples-over-time often called frames and that is key mechanism for rapid FIL simulation since the overhead cost is lower when using a large vector size. For video, an entire frame including the blanking intervals is a good choice for the vector size to make simulation faster. You can see that here under the heading "Modified FIL Model for Pixel Streaming"
What you really need to do is run the FIL Wizard in HDL Verifier to create the correct FIL block (doc here). This wizard works with either generated or hand-written HDL code and lets you set the port properties. That is the best way to get a FIL block your Xilinx median filter.
I would also mention that the Vision HDL Toolbox has median filters in various sizes and many other FPGA video processing functions that are platform independent.
If this doesn't answer your question completely, I think you should write again with your actual goal--is it simulation acceleration via FPGA? FIL does not always accelerate a design since there is overhead in moving data back and forth so care needs to be taken in the architecture of the design in that case.
-Brian
andrew kurtz
andrew kurtz el 10 de En. de 2019
I have solved the problem:
My problem was the HDL compiler was unable to compile due to the "frame to pixel" output to the filter input due to the control signal being bussed incorrectly. I was using a standard MUX block, but was finally able to compile it using the "Pixel Control Bus Creator" block.
Sorry if my initial question was unclear.
Thanks.

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