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Simulink Design Verifier Dead Logic

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galaxy
galaxy on 14 Nov 2019
Answered: Andrew LeCours on 3 Dec 2019
I used simulink design verifier to check my state machine model. And some dead logics are detected.
8.PNG
Red line is dead logic, data type of input1 and input2 are int16.
Simulink Design Verifier explain that some conditions can only be true or unreadchable such as following.
9.PNG
Could you please explain to me??

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Answers (1)

Andrew LeCours
Andrew LeCours on 3 Dec 2019
can only be true means that the specified condition under Description is always true. For example, for the dead logic in the second row of the report, input1 < input2 is always true, which means that the condition, when evaluated, never evaluates to false. The reason that this is the case, is that the (input1 < input2) || (input1 == 0) condition is only evaluated when transition 1, input1 >= input2 is false (hence ~(input1 >= input2) is true), which guarantees that input1 < input2 will be true. For more information, see transition execution rules.
unreachable means that the specified condition never executes. In this case, the objectives involving substate A2 are all unreachable, because the transition (input1 < input2) || (input1 == 0) causes the state to be exited, and then re-entered. This resets the state, forcing the substate back to A1. Thus, the state A2 is never actually used by the chart.

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