How do I reduce resource utilization for an AXI4-Stream interface generated using HDL Coder?

We are trying to use HDL Coder AXI4-Stream interfaces with our Simulink model instead of discrete input and outputs. We noticed that HDL Coder created some extra FIFO logic for the AXI4-Stream Master and Slave interfaces when we checked the generated VHDL files. Is there a way to edit the size of these FIFOs, and how can we remove them if we don’t want to use them?

Answer 1

[MathWorks Support Team]

The extra FIFO logic is present in the generated code because HDL Coder offers users a way of implementing a simplified AXI4-Stream protocol, which makes the modeling of signals such as READY optional. Here is a documentation page with more information:

https://www.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-stream-interface-generation.html

The FIFOs inserted by the AXI4-Stream interface are very minimal (approximately a depth of 4), so they shouldn’t consume too many resources.

However, if you still need to minimize these resources, you can eliminate the FIFOs by modeling the full protocol including the VALID/READY handshaking. There are two possible approaches:

(1) Create your own reference design and add an Internal IO interface instead of an AXI4-Stream interface:

https://www.mathworks.com/help/hdlcoder/ref/hdlcoder.referencedesign.addinternaliointerface.html

The resulting block design would directly wire the DUT ports to the AXI4-Stream interface in the reference design. It would not package the ports as a Vivado bus interface (however, some post-processing in Vivado could accomplish this).

(2) You can also use standalone IP core generation (i.e. no reference design, target platform set to “Generic Xilinx Platform”) and map the AXI4-Stream signals to “External Port”. Then, you can just integrate the IP core manually into a larger Vivado design.

This will generate the IP core with the TDATA, TVALID, etc exposed as regular ports at the top level. Then, you can open the generated Vivado IP Packager project (hdl_prj/ipcore/<ip name>/prj_ip/prj_ip.xpr) and remap these ports to an AXI4-Stream interface port. There’s an “automap interfaces” button in the IP Packager GUI that should recognize these automatically. For the automap to work, you would have to give the ports in Simulink names like M_AXIS_TDATA, M_AXIS_TVALID, etc. For more information, consult the Vivado User's Guide.