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Use Target Hardware Instruction Set Extensions to Generate SIMD Code from Simulink Blocks for ARM Cortex-A Processors

Note

This workflow requires an Embedded Coder® license.

This topic shows how to generate single instruction, multiple data (SIMD) code from Simulink® blocks by using the model configuration parameter Leverage target hardware instruction set extensions and the Embedded Coder Support Package for ARM® Cortex®-A Processors. You can also generate SIMD code by using the code replacement library ARM Cortex-A, as described in Optimize Code for ARM Cortex-A Processors (Embedded Coder). The code replacement library also applies other optimizations, whereas using the configuration parameter applies only SIMD optimizations.

  1. Open the Embedded Coder app from the Apps gallery in the Simulink model toolstrip.

  2. In the C Code tab, select Settings > Hardware Implementation.

  3. Select a hardware target that supports SIMD code generation. Set these parameters:

    • Hardware board (Simulink) — None or select a hardware board that results in the following device vendor and type settings.

    • Device vendor (Simulink) — ARM Compatible

    • Device type (Simulink) — ARM Cortex-A (32-bit) or ARM Cortex-A (64-bit).

  4. On the Code Generation > Optimization pane, from the Leverage target hardware instruction set extensions (Simulink Coder) list, select the instruction set extension supported by your processor. For this example, select Neon v7.

  5. Optionally, select the Optimize reductions (Simulink Coder) parameter to generate SIMD code for reduction operations or the FMA (Simulink Coder) parameter to generate SIMD code for fused multiply-add operations.

  6. On the Code Generation > Interface pane, under Software environment, set Code replacement libraries to None, and clear Support non-finite numbers.

  7. Depending on the blocks you use in your model, you might have to change additional block-level settings to generate SIMD code using this workflow. For more information on these settings, see the Extended Capabilities : C/C++ Code Generation sections in the respective block reference pages.

  8. Generate code from the model.

The SIMD instructions are the intrinsic functions that start with the identifier v in the generated code. These functions process multiple data in a single iteration of the loop because the loop increments by four for single data types and by two for double data types. For models that process more data and are computationally more intensive, the SIMD instructions can significantly speed up the code execution time.

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