QSPI Controller Peripheral Configuration
Map QSPI controller peripherals in the Infineon AURIX model to peripheral registers in the MCU
Since R2024a
Description
View and edit the map of peripherals in the Infineon® AURIX™ model to the hardware peripherals.
Using the Peripheral Configuration tool, you can:
View and edit configuration parameters for QSPI controller block.
Configure the global parameters. To set the group peripheral, select peripheral in Browser > Peripherals >
QSPI Controller
. For more, see Map Tasks and Peripherals Using Hardware Mapping.Check for any conflicts between peripherals.
Open the QSPI Controller Peripheral Configuration
In the Simulink toolstrip, go to Hardware tab and click Hardware Mapping.
Parameters
Enable Tx FIFO event
— Option to enable QSPI transmit buffer interrupt
off
(default) |
on
Enables the QSPI transmit FIFO interrupt.
When you select this option, the dialog box displays the Tx FIFO Mode Selection options.
Note
Enabling this parameter, expect that the data is handled through interrupts. Therefore it is mandatory to use QSPI Peripheral block (Transfer mode as SPI Transmit) or QSPI Controller (Transfer mode as SPI Transmit or SPI Transmit and Receive) block during the events.
Tx FIFO mode
— FIFO flag mode setting for Tx FIFO buffer
Batch Move
(default) |
Single Move
This parameter is read-only.
Select one of these operation modes for Tx FIFO buffer:
Single Move —
Select this mode to generate an interrupt to refill the transmit buffer as soon as there is a free element.Batch Move —
Select this mode to generate an interrupt if the FIFO level of Tx data exceeds above programmed threshold.
Dependencies
To enable this parameter, select the Enable Tx FIFO event parameter.
Tx FIFO threshold
— FIFO level for Tx FIFO event
1
(default) |
2
|
3
|
4
Specify FIFO level for Tx FIFO event.
Dependencies
To enable this parameter, select the Enable Tx FIFO event parameter.
Enable Rx FIFO event
— Option to enable receive buffer interrupt
off
(default) |
on
Enables the QSPI receive FIFO interrupt.
When you select this option, the dialog box displays the Rx FIFO Mode Selection options.
Note
Enabling this parameter, expect that the data is handled through interrupts. Therefore it is mandatory to use QSPI Peripheral block (Transfer mode as SPI Receive) or QSPI Controller block (Transfer mode as SPI Receive or SPI Transmit and Receive) during the events.
Rx FIFO mode
— FIFO flag mode setting for receive buffer
Batch Move
(default) |
Single Move
This parameter is read-only.
Select one of these operation modes for receive buffer:
Single Move —
Select this mode to generate an interrupt to fetch the received element as soon as possible.Batch Move —
Select this mode to generate an interrupt if the filling level rises above the programmed threshold.
Dependencies
To enable this parameter, select the RxFifo event parameter.
Rx FIFO threshold
— FIFO level for Rx FIFO event
0
(default) |
1
|
2
|
3
Specify FIFO level for Rx FIFO event.
Dependencies
To enable this parameter, select the Enable Rx FIFO event parameter.
Enable error event
— Option to enable error interrupt
off
(default) |
on
Enables the QSPI error interrupt.
Note
Enabling this parameter, expects that the data is handled through interrupts. Therefore it is recommended to use QSPI block (SPI receive or transmit as transfer mode) during the events.
Serial Clock pin (SCK)
— Pin selection for serial clock
pin numbers
Select the QSPI serial clock pin selection. The available pin numbers vary based on the module selected.
Serial Data Out pin (SDO)
— QSPI serial data out pin selection
pin numbers
Select the QSPI serial data out pin selection. The available pin numbers vary based on the module selected.
Serial Data In pin (SDI)
— QSPI serial data input pin selection
pin numbers
Select the QSPI serial data input pin selection. The available pin numbers vary based on the module selected.
Input pins pull
— Input pull for QSPI pin
Pull-down
(default) | Tri-state
| Pull-up
Select input pull for QSPI pin.
Output pins strenght
— Drive strength for output pin
Push pull
(default) | Open-drain
Select drive strength for output pin.
Speed
— Speed for QSPI pin
Speed-1
(default) | Speed-2
| Speed-3
| Speed-4
Select the pin speed for QSPI.
Voltage level
— Voltage level for QSPI pin
Automotive
(default) | TTL-5V
| TTL-3.3V
Select voltage level of QSPI pin.
Module
— Option to select the controller module
0
(default) | 1
| 2
| ...
Select the QSPI controller module 0
through
4
on the hardware board.
Tx mode
— QSPI transmit mode
Continuous
(default) | Single transfer
Select the QSPI transmit mode.
Continuous
- This option activates the chip select signal till the data transfer completes.Single-transfer
- This option deactivates the chip select signal for every data element involved in the data transfer.
Baud rate
— Configure baud rate for SPI transaction
1000000
(default) | positive scalar integer
Specifies the rate of data communication between the peripherals connected (clock period).
Data heading (Endianness)
— QSPI data heading in binary
MSB first
(default) | LSB first
Select the QSPI data heading in binary numbers.
MSB first
- the bit furthest to the left (msb) is moved first from SDO pin followed by the subsequent left bits.LSB first
- the bit furthest to the right (lsb) is moved first from SDO pin followed by the subsequent right bits.
Polarity
— Clock polarity in idle state
Idle low
(default) | Idle High
Select the QSPI clock polarity in idle state.
Phase
— QSPI clock phase
Trailing edge
(default) | Leading edge
Select the QSPI clock phase.
Enable parity
— Enable QSPI clock parity
off
(default) | on
Enables the QSPI clock parity.
When you select the Enable parity parameter, the dialog box displays the Parity parameter.
Parity
— Clock parity bit type
Even parity
(default) | Odd parity
Select the QSPI clock parity.
Dependencies
To enable Parity parameter, select the Enable parity parameter.
Enable simplex
— Option to enable simplex communication
off
(default) | on
Enable to configure the QSPI Controller block to either transmit or receive data at a time. Disable to use for both transmit and receive at a time.
CS pin
— QSPI chip select pin
options vary based on the module selected
Select the QSPI chip select pin.
CS active level
— QSPI chip select active levels
Low
(default) | High
Select the QSPI chip select active level.
CS lead delay
— QSPI chip select lead delay
0.0
(default) | 0.5
| 1
| 1.5
| 2
| 2.5
| 3
| 3.5
Introduces the selected delay between the active edge of the CS pin and the first shift clock edge.
CS trail delay
— QSPI chip select trail delay
0.0
(default) | 0.5
| 1
| 1.5
| 2
| 2.5
| 3
| 3.5
Introduces the selected delay between shift clock period of a data block and is followed either by the deactivating edge of CS pin, or a new data block in continuous mode.
CS inactive delay
— QSPI chip select inactive delay
0.0
(default) | 0.5
| 1
| 1.5
| 2
| 2.5
| 3
| 3.5
Introduces the selected delay between the end of the last trail phase of a frame.
Version History
Introduced in R2024a
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