HDL Coder
HDL Coder™ generates portable, synthesizable VHDL® and Verilog® code from MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code can be used for FPGA programming or ASIC prototyping and design.
HDL Coder provides a workflow advisor that automates the programming of Xilinx®, Microsemi®, and Intel® FPGAs. You can control HDL architecture and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated Verilog and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.
Support for industry standards is available through IEC Certification Kit (for ISO 26262 and IEC 61508).
Get Started
Learn the basics of HDL Coder
HDL Code Generation from MATLAB
Generate HDL Code from MATLAB algorithms
SystemC Code Generation from MATLAB
Generate SystemC Code from MATLAB algorithms
HDL Code Generation from Simulink
Generate HDL code from Simulink models
Targeting FPGA & SoC Hardware
Deploy generated HDL code on a target hardware platform
HDL Coder Supported Hardware
Support for third-party hardware, such as Intel, Microchip, and Xilinx FPGA boards
Tool Qualification and Certification
Qualify HDL Coder for IEC certification