This example shows how to build a reference design to run an audio algorithm and access audio input and output on ZYBO board.
To run this example, you must have the following software and hardware installed and set up:
HDL Coder Support Package for Xilinx Zynq Platform
Embedded Coder Support Package for Xilinx Zynq Platform
Xilinx Vivado, with latest version mentioned in the documentation
Digilent® Zybo Zynq™ development board with the accessory kit
Note: This example uses Digilent® Zybo Zynq-7000 ARM/FPGA SoC trainer board. This example does not work on Digilent® Zybo Z7: Zynq-7000 ARM/FPGA SoC development board which have two variants Zybo Z7-10 and Zybo Z7-20.
To setup the ZYBO board, refer to the Set up the Zybo board section in the Define Custom Board and Reference Design for Zynq Workflow article.
In this example you will create a reference design which receives audio input from ZYBO board, performs some processing on it and transmits the processed audio data out of ZYBO board. You also generate IP cores for peripheral interfaces using HDL Workflow Advisor.
To perform audio processing on ZYBO board, following 2 protocols are needed:
I2C to configure the SSM2603 audio codec chip on ZYBO board.
I2S to stream the digitized audio data between the codec chip and zynq fabric.
The above figure is a high level architecture diagram that shows how the reference design is used by the Filtering Algorithm IP on ZYBO board. This example is similar to the audio system reference design for Zedboard except that the ZYBO board uses a SSM2603 audio codec chip where as the Zedboard uses ADAU1761 audio codec chip. Rest of the operating parameters are same as the Audio System reference design for Zedboard. For more details, please refer to Authoring a Reference Design for Audio System on a Zynq Board example.
The following steps are used to create the reference design described above:
Generate IP Cores for peripheral interfaces
Create a custom audio codec reference design in Vivado
Create the reference design definition file
Verify the reference design
In this example,
I2C IP is developed using stateflow blocks & legacy VHDL code for tristate buffer.
I2S IP is developed by modelling it in Simulink.
For creation of I2C IP to configure Audio Codec SSM2603, refer to IP Core Generation of an I2C Controller IP to Configure the Audio Codec Chip article.
Design a model in Simulink with a matlab function which implements the I2S protocol.
modelname = 'hdlcoder_I2S_ssm2603'; open_system(modelname);
Testing and IP core generation steps are same as Zedboard I2S model. For generation of I2S IP, see Authoring a Reference Design for Audio System on a Zynq Board example.
I2C, I2S and FIFO IPs are incorporated in the custom reference design. To create a custom reference design, refer to the "Create and export a custom reference design using Xilinx Vivado" section in Define Custom Board and Reference Design for Zynq Workflow.
Key points to be noted while creating this custom reference design:
We must understand the theory of operation of the audio codec chip on the ZYBO board.
The FIFOs are set to default values for their configuration.
For the IP cores generated using HDL Workflow Advisor, IPCORE_CLK and AXI4_Lite_ACLK should be connected to the same clock source.
On validating the block design in Vivado, there should be no critical warnings except for the unconnected ports.
In this reference design, the audio codec is configured to operate in the Master mode.
The following signals run between the reference design on Zynq Soc and the audio codec on ZYBO board:
Bit_clock is the product of the sampling frequency, the number of bits per channel and the number of channels. It is driven by the audio codec in master mode. In this example, Sampling frequency is 48KHz, No of channels is 2, Number of bits per channel is 24.
Serial_data_in is the analog to digital converted audio data from the codec.
Serial_data_out is the digital audio data going to codec to be converted into analog form.
I2C_CLK and I2C_DATA are standard I2C signals
MUTEN is the Hardware mute pin connected to audio codec SSM2603.
MCLK is the 12.288MHz clock signal required by the codec.
The custom audio codec reference design created for this example is shown below:
The following code describes the contents of the ZYBO board reference design definition file plugin_rd.m for the above reference design. For more details on how to define and register custom board, refer to Define Custom Board and Reference Design for Zynq Workflow example.
Go to ZYBO folder using the following command:
cd ([matlabroot '/toolbox/hdlcoder/hdlcoderdemos/customboards/ZYBO']);
All files that are required for the reference design such as IP core files, XDC files, plugin_rd file etc should be added to the matlab path, inside ZYBO folder using the hierarchy shown below. The user generated IP core files should be in +vivado folder. plugin_rd.m, tcl files and xdc files should be in +vivado_audio_filter_2017_2 folder.
To verify the reference design, to generate Audio Filter IP core from a model and integrate it with the audio codec reference design, refer to Running an Audio Filter on Live Audio Input Using a Zynq Board example.