Deploy Simscape™ Plant Models to Speedgoat FPGA I/O Modules

This example shows how you can deploy the Simscape plant models on Speedgoat FPGA I/O modules by using the HDL Workflow Advisor. This workflow is a two-step process.

  1. Develop the Simscape model and convert it into an implementation model by using the Simscape HDL Workflow Advisor. HDL code is generated from this implementation model. For more information, see Generate HDL Code for Simscape Models.

  2. Deploy HDL code to a Speedgoat I/O module by using the HDL Workflow Advisor.

Why Deploy a Simulink Model to Speedgoat FPGA Modules

You can use the HDL Workflow Advisor to deploy the Simulink™ model to Speedgoat FPGA I/O modules. Simulating the plant model on the FPGA provides:

  • Real-time Simulation: Hardware-in-the-loop provides real-time simulation of your Simscape plant model.

  • Hardware Acceleration: The speed of simulating physical systems increases by implementing it on hardware as reconfigurable FPGAs provide rapid hardware prototyping. You can use this capability to model complex physical systems.

Set Up and Configuration

To deploy the Simscape plant models onto Speedgoat FPGA modules:

1. Install Xilinx Vivado®

Speedgoat FPGA IO333-325K uses Xilinx Vivado. If it is not already present, install Xilinx Vivado v2018.2. Then, set the tool path to the installed Xilinx Vivado 2018.2 executable. To set the tool path, use the hdlsetuptoolpath function.

hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','C:\Xilinx\Vivado\2018.2\bin\vivado.bat')

2. Set Up I/O Module

To run the simulation of the Simscape plant model in real time on hardware, you must set up the I/O module. For information on setting up the I/O module, see Xilinx HDL Software for Speedgoat I/O Hardware.

HDL Workflow Advisor

The HDL Workflow Advisor guides you through the stages of generating HDL code for a Simulink subsystem and the FPGA design process, such as:

  • Checking the model for HDL code generation compatibility and automatically fixing incompatible settings.

  • Generating HDL code, a test bench, and scripts to build and run the code and test bench.

  • Synthesis and timing analysis through integration with third-party synthesis tools.

  • Completing the automated workflows for deployment on hardware platforms such as System-on-Chip(SoC), FPGAs, and Speedgoat I/O modules.

This example shows how to use the HDL Workflow Advisor to deploy HDL code on Speedgoat IO333-325K module that uses Xilinx Vivado. For example, to open the HDL Workflow Advisor for a Subsystem inside the model, enter:


For more information, see hdladvisor.

In the HDL Workflow Advisor, the left pane lists the folders in the hierarchy. Each folder represents a group or category of related tasks. Expanding the folders shows the available tasks in each folder. From the left pane, you can select a folder or an individual task. The HDL Workflow Advisor displays information about the selected folder or task in the right pane. The contents of the right pane depends on the selected folder or task. For some tasks, the right pane contains simple controls for running the task and a display area for status messages and other task results. For other tasks that involve setting code or test bench generation parameters, the right pane displays several parameter and option settings.

To learn more about each individual task, right-click that task, and select What's This?.

For more information, see Getting Started with the HDL Workflow Advisor.

Two Level Ideal Converter Model

This example uses a Two-Level Ideal converter Simscape plant model. To open this model, enter:


Save this model locally as TwoLevelConverter_HDL.slx to run this workflow.



The Simscape subsystem receives six-switch controlling pulses as input. The Simscape subsystem acts as a generator that uses a two-level, carrier-based PWM method to:

  1. Sample a reference wave.

  2. Compare the sample to a triangular carrier wave.

  3. Generate a switch-on pulse if a sample is higher than the carrier signal or a switch-off pulse if a sample is lower than the carrier wave.

Generate HDL Implementation Model

To generate an implementation model, use the Simscape HDL Workflow Advisor. Run the sschdladvisor function for your model:

### Running Simscape HDL Workflow Advisor for <a href="matlab:(TwoLevelConverter_HDL)">TwoLevelConverter_HDL</a>

To generate the implementation model, in the Simscape HDL Workflow Advisor, keep the default settings for all the tasks, and then run the tasks. You see a link to the model in the Generate implementation model task.

The Implementation Model

To open the implementation model, enter:


The model contains two subsystems. The HDL Subsystem models the state-space representation that you generated from the Simscape model. The ports of this subsystem use the same name as the Simulink-PS Converter and PS-Simulink Converter blocks that you use in your original Simscape model. If you navigate inside this Subsystem, you see several delays, adders, and Matrix Multiply blocks that model the state-space equations. From and Goto blocks inside this subsystem provide the same input as that of the original model to the HDL Subsystem.

Deploy Two Level IGBT Converter Model to Speedgoat IO333-325K Module

This example shows how to deploy the implementation model of Two Level IGBT Converter to Speedgoat IO333-325K FPGA module by using the HDL Workflow Advisor. The Speedgoat IO333 FPGA module uses Xilinx Vivado and IP Core Generation Infrastructure. Before you run the Workflow Advisor, make sure that you have specified the path to the installed Xilinx Vivado executable.

1. Open HDL Workflow Advisor

To open the HDL Workflow Advisor for the Implementation model, enter:

hdladvisor('gmStateSpaceHDL_TwoLevelConverter_HDL/HDL Subsystem')

2. In Set Target Device and Synthesis Tool task, set these parameters and select Run This Task:

  • Target workflow as Simulink Real-Time FPGA I/O

  • Target platform as Speedgoat IO333-325K

  • Synthesis tool as Xilinx Vivado

3. In Set Target Reference Design task, select a value of x4 for the parameter PCIe lanes, and select Run This Task.

4. In Set Target Interface task, map the Input and Output single data type ports to PCIe Interface and select Run This Task.

5. In Set Target Frequency task, select a target frequency that is within the range. If the target frequency is set to higher values, it results in a failure to generate the bitstream when you run task Build FPGA Bitstream. This example has Target Frequency set to 50 MHz.

6. Right-click Generate RTL Code and IP Core task and select Run to Selected Task. This step generates a warning if the model uses vector data types. Click the link in the warning, select Scalarize vector ports, and rerun the task.

7. Run the workflow to the Generate Simulink Real-Time interface task. In Create Project task, you can open the Vivado project and see the implemented design.

8. When the Generate Simulink Real-Time interface task passes, you see a link to open the Simulink Real-Time Interface Model. Select this link.

Export HDL Workflow to Script

Optionally, you can:

  • Save the HDL Workflow Advisor settings to script and run the script using command line.

  • Import the settings to modify it and rerun it using the HDL Workflow Advisor User Interface.

Export an HDL Workflow Script

  1. In the HDL Workflow Advisor, configure and run all the tasks.

  2. Select File > Export to Script.

  3. In the Export Workflow Configuration dialog box, enter a file name and save the script.

The script is a MATLAB® file that you can run from the command line.

Import an HDL Workflow Script

  1. In the HDL Workflow Advisor, select File > Import from Script.

  2. In the Import Workflow configuration dialog box, select the script file and click Open.

The HDL Workflow Advisor updates the tasks with the imported script settings.

Simulink Real-Time FPGA I/O Workflow Example

This example shows how to configure and run an exported HDL Workflow script.

To generate an HDL Workflow script, configure and run the HDL Workflow Advisor with your Simulink design, then export the script.

This script is a Simulink Real-Time FPGA I/O workflow script that targets the Speedgoat IO333-325K module, which uses the Xilinx Vivado synthesis tool.

To edit the exported script in MATLAB command window, enter:


See Also


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