Verify Code with HDL Test Bench

Simulate the generated HDL design under test (DUT) with test vectors from the test bench using the specified simulation tool.

  1. Start the MATLAB to HDL Workflow Advisor.

  2. At step HDL Verification, click Verify with HDL Test Bench.

  3. Select Generate HDL test bench.

    This option enables HDL Coder™ to generate HDL test bench code from your MATLAB® test script.

  4. Optionally, select Simulate generated HDL test bench. This option enables MATLAB to simulate the HDL test bench with the HDL DUT.

    If you select this option, you must also select the Simulation tool.

  5. For Test Bench Options, select and set the optional parameters according to the descriptions in the following table.

    HDL Test Bench ParameterDescription
    Test bench name postfixSpecify the postfix for the test bench name.
    Force clockEnable for test bench to force clock input signals.
    Clock high time (ns)Specify the number of nanoseconds the clock is high.
    Clock low time (ns)Specify the number of nanoseconds the clock is low.
    Hold time (ns)Specify the hold time for input signals and forced reset signals.
    Force clock enableEnable to force clock enable.
    Clock enable delay (in clock cycles)Specify time (in clock cycles) between deassertion of reset and assertion of clock enable.
    Force resetEnable for test bench to force reset input signals.
    Reset length (in clock cycles)Specify time (in clock cycles) between assertion and deassertion of reset.
    Hold input data between samplesEnable to hold subrate signals between clock samples.
    Input data interval

    Specifies the number of clock cycles between assertions of clock enable. For more information, see Specify Test Bench Clock Enable Toggle Rate.

    Initialize test bench inputsEnable to initialize values on inputs to test bench before test bench drives data to DUT.
    Multi file test benchEnable to divide generated test bench into helper functions, data, and HDL test bench code.
    Test bench data file name postfixSpecify the character vector to append to name of test bench data file when generating multi-file test bench.
    Test bench reference postfixSpecify the character vector to append to names of reference signals in test bench code.
    Ignore data checking (number of samples)Specify the number of samples at the beginning of simulation during which output data checking is suppressed.
    Simulation iteration limitSpecify the maximum number of test samples to use during simulation of generated HDL code.
  6. Optionally, select Skip this step if you don’t want to use the HDL test bench to verify the HDL DUT.

  7. Click Run.

    If the test bench and simulation is successful, you should see messages similar to these in the message pane:

    ### Begin TestBench generation.
    ### Collecting data...
    ### Begin HDL test bench file generation with logged samples
    ### Generating test bench: mlhdlc_sfir_fixpt_tb.vhd
    ### Creating stimulus vectors...
    ### Simulating the design 'mlhdlc_sfir_fixpt' using 'ModelSim'.
    ### Generating Compilation Report mlhdlc_sfir_fixpt_vsim_log_compile.txt
    ### Generating Simulation Report mlhdlc_sfir_fixpt_vsim_log_sim.txt
    ### Simulation successful.
    ### Elapsed Time: 113.0315 sec(s)

    If there are errors, those messages appear in the message pane. Fix errors and click Run.