generatehdl

Generate HDL code for quantized filter (To be removed)

generatehdl function will be removed in a future release. Instead, use the DSP HDL IP Designer (DSP HDL Toolbox) app, System objects, or Simulink^® blocks from DSP HDL Toolbox™. To generate HDL code from DSP HDL Toolbox algorithms, you must also have the HDL Coder™ product.

Syntax

generatehdl(filtSO,'InputDataType',nt)

generatehdl(filtSO,'InputDataType',nt,'FractionalDelayDataType',fd)

generatehdl(filterObj)

generatehdl(___,Name,Value)

Description

generatehdl(filtSO,'InputDataType',nt) generates HDL code for the specified filter System object™ and the input data type, nt.

The generated file is a single source file that includes the entity declaration and architecture code. You can find this file in your current working folder, inside the hdlsrc subfolder.

generatehdl(filtSO,'InputDataType',nt,'FractionalDelayDataType',fd) generates HDL code for a dsp.VariableFractionalDelay filter System object. Specify the input data type, nt, and the fractional delay data type, fd.

generatehdl(filterObj) generates HDL code for the specified dfilt filter object using default settings.

generatehdl(___,Name,Value) uses optional name-value arguments, in addition to the input arguments in previous syntaxes. Use these properties to override default HDL code generation settings.

• To customize filter name, destination folder, and to specify target language, see Fundamental HDL Code Generation Properties.

• To configure coefficients, complex input ports, and optional ports for specific filter types, see HDL Filter Configuration Properties.

• To optimize the speed or area of generated HDL code, see HDL Optimization Properties.

• To customize ports, identifiers, and comments, see HDL Port and Identifier Properties.

• To customize HDL constructs, see HDL Construct Properties.

• To generate and customize test bench, see HDL Test Bench Properties.

• To integrate third-party EDA tools into the filter design workflow, see HDL Synthesis and Workflow Automation Properties.

Examples

Generate HDL Code and Test Bench for FIR Equiripple Filter

Design a direct form symmetric equiripple filter with these specifications:

• Normalized passband frequency of 0.2

• Normalized stopband frequency of 0.22

• Passband ripple of 1 dB

• Stopband attenuation of 60 dB

The design function returns a dsp.FIRFilter System object™ that implements the specification.

filtSpecs = fdesign.lowpass('Fp,Fst,Ap,Ast',0.2,0.22,1,60);
FIRe = design(filtSpecs,'equiripple','FilterStructure','dfsymfir','SystemObject',true)

FIRe = 
  dsp.FIRFilter with properties:

            Structure: 'Direct form symmetric'
      NumeratorSource: 'Property'
            Numerator: [-0.0011 -0.0017 -0.0025 -0.0031 -0.0031 -0.0024 -9.7703e-04 0.0010 0.0031 0.0049 0.0059 0.0057 0.0046 0.0029 9.8747e-04 -3.9494e-04 -8.8308e-04 -3.8937e-04 8.1727e-04 0.0022 0.0032 0.0033 0.0025 9.6853e-04 … ] (1×202 double)
    InitialConditions: 0

  Show all properties

Generate VHDL code and a VHDL test bench for the FIR equiripple filter. When the filter is a System object, you must specify a fixed-point data type for the input data type. The coder generates the files MyFilter.vhd and MyFilterTB.vhd in the default target folder, hdlsrc.

generatehdl(FIRe,'InputDataType',numerictype(1,16,15),'Name','MyFilter',...
    'GenerateHDLTestbench','on','TestBenchName','MyFilterTB')

### Starting VHDL code generation process for filter: MyFilter
### Generating: C:\Users\nhunting\ExampleManager\nhunting.Bdoc24b.j2736925\hdlfilter-ex63281302\hdlsrc\MyFilter.vhd
### Starting generation of MyFilter VHDL entity
### Starting generation of MyFilter VHDL architecture
### Successful completion of VHDL code generation process for filter: MyFilter
### HDL latency is 2 samples
### Starting generation of VHDL Test Bench.
### Generating input stimulus
### Done generating input stimulus; length 4486 samples.
### Generating Test bench: C:\Users\nhunting\ExampleManager\nhunting.Bdoc24b.j2736925\hdlfilter-ex63281302\hdlsrc\MyFilterTB.vhd
### Creating stimulus vectors ...
### Done generating VHDL Test Bench.

Generate Partly Serial FIR Filter with Programmable Coefficients

Create a direct form antisymmetric filter with coefficients:

coeffs = fir1(22,0.45);
firfilt = dsp.FIRFilter('Numerator',coeffs,'Structure','Direct form antisymmetric')

firfilt = 
  dsp.FIRFilter with properties:

            Structure: 'Direct form antisymmetric'
      NumeratorSource: 'Property'
            Numerator: [3.6133e-04 0.0031 8.4473e-04 -0.0090 -0.0072 0.0203 0.0272 -0.0341 -0.0794 0.0455 0.3078 0.4490 0.3078 0.0455 -0.0794 -0.0341 0.0272 0.0203 -0.0072 -0.0090 8.4473e-04 0.0031 3.6133e-04]
    InitialConditions: 0

  Show all properties

To generate HDL code, call the generatehdl function. When the filter is a System object, you must specify a fixed-point data type for the input data. To generate a partly serial architecture, specify a serial partition. To enable CoefficientMemory property, you must set CoefficientSource to ProcessorInterface.

generatehdl(firfilt,'InputDataType',numerictype(1,16,15), ...
    'SerialPartition',[7 4],'CoefficientMemory','DualPortRAMs', ...
    'CoefficientSource','ProcessorInterface')

### Starting VHDL code generation process for filter: firfilt
### Generating: C:\Users\nhunting\ExampleManager\nhunting.Bdoc24b.j2736925\hdlfilter-ex21465785\hdlsrc\firfilt.vhd
### Starting generation of firfilt VHDL entity
### Starting generation of firfilt VHDL architecture
### Clock rate is 7 times the input sample rate for this architecture.
### Successful completion of VHDL code generation process for filter: firfilt
### HDL latency is 3 samples

The generated code includes a dual-port RAM interface for the programmable coefficients.

Input Arguments

filtSO — Filter

filter System object

Filter from which to generate HDL code, specified as a filter System object. To create a filter System object, use the design function or see the reference page of the object. You can use the following System objects from DSP System Toolbox™:

Single Rate Filters

• dsp.FIRFilter

• dsp.HighpassFilter

• dsp.LowpassFilter

• dsp.FilterCascade

• dsp.VariableFractionalDelay

Multirate Filters

• dsp.FIRDecimator

• dsp.FIRInterpolator

• dsp.FIRRateConverter

• dsp.FarrowRateConverter

• dsp.CICDecimator

• dsp.CICInterpolator

• dsp.CICCompensationDecimator

• dsp.CICCompensationInterpolator

• dsp.FilterCascade

• dsp.DigitalDownConverter (supports the generatehdl function, but does not support fdhdltool and the Generate HDL dialog window)

• dsp.DigitalUpConverter (supports the generatehdl function, but does not support fdhdltool and the Generate HDL dialog window)

nt — Input data type

numerictype object

Input data type, specified as a numerictype object. This argument applies only when the input filter is a System object. Call numerictype(s,w,f), where s is 1 for signed and 0 for unsigned, w is the word length in bits, and f is the number of fractional bits.

fd — Fractional delay data type

numerictype object

Fractional delay data type, specified as a numerictype object. This argument applies only when the input filter is a dsp.VariableFractionalDelay System object. Call numerictype(s,w,f), where s is 1 for signed and 0 for unsigned, w is the word length in bits, and f is the number of fractional bits.

filterObj — Filter

dfilt object

Filter from which to generate HDL code, specified as a dfilt object. You can create this object by using the design function. For an overview of supported filter features, see Filter Configuration Options.

Alternatives

You can use the fdhdltool function to generate HDL code instead (requires Filter Design HDL Coder™). Specify the input and fractional delay data types as arguments, and then set additional properties in the Generate HDL dialog box.

Version History

Introduced before R2006a