Sequence Feedback
R2026bLibraries:
HDL Verifier /
For Use with DPI-C SystemVerilog
Description
Add-On Required: This feature requires the ASIC Testbench for HDL Verifier add-on.
The Sequence Feedback block promotes a feedback signal from the scoreboard
to the sequence in a UVM testbench model. The block implements a Unit
Delay (Simulink) block with the Initial condition parameter set to
0.
Ports
Input
Output
Programmatic Use: Add Block
To add the block programmatically, use the add_block function with one of these library block paths as the source.
"dpiblklib/Sequence Feedback"
Example: add_block("dpiblklib/Sequence Feedback","myModel/myBlock",MakeNameUnique="on")
Version History
Introduced in R2023a