Sequence Feedback

Connect between scoreboard and sequence in UVM testbench model

Since R2023a

Add-On Required: This feature requires the ASIC Testbench for HDL Verifier add-on.

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Libraries:
HDL Verifier / For Use with DPI-C SystemVerilog

Description

The Sequence Feedback block promotes a feedback signal from the scoreboard to the sequence in a UVM testbench model. The block implements a Unit Delay (Simulink) block with the Initial condition parameter set to 0.

Ports

Input

Port_1 — Feedback signal from scoreboard subsystem

scalar

The Sequence Feedback block accepts an input signal directly from the scoreboard subsystem.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

Output

Port_1 — Feedback signal to sequence subsystem

scalar

The Sequence Feedback block outputs a signal directly to the sequence subsystem.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

Version History

Introduced in R2023a