Manual Hardware Setup

You can use FPGA-in-the-loop (FIL), FPGA data capture, or AXI manager via Ethernet, JTAG, and PCI Express^® connections. You can use FIL or AXI manager via USB Ethernet connection for an AMD^® Zynq^® board. Some FPGA boards support multiple connection methods, and some boards support only one method. Choose setup instructions based on the connection method you plan to use for FIL simulation.

When possible, use the guided setup. To run the support package setup, or modify your installation:

On the MATLAB^® Home tab, in the Environment section, select Help > Check for Updates.

For more about the guided setup, see Guided Hardware Setup.

Step 1. Set Up FPGA Development Board

JTAG or Ethernet Connection

1. Make sure that the board power switch is OFF during these setup steps.

2. Make sure that all jumpers on the FPGA development board are in the factory default position.

3. Connect the AC power cord to the power plug.

4. Plug the power supply adapter cable into the FPGA development board.

5. Connect the JTAG cable to the FPGA development board and the computer. When you use Ethernet for FIL simulation, the JTAG cable is still required to program the FPGA.

6. If you plan to use an Ethernet connection for FIL simulation, connect the crossover Ethernet cable between the FPGA development board and the Ethernet adapter on your computer.

7. Turn on the power switch on the FPGA board.

PCI Express Connection

1. Make sure that the board power switch is OFF during these setup steps.

2. Select the maximum number of PCI Express (PCIe) lanes supported by the board. to Refer to the user manual for the board for details.

   Supported Board	PCI Express Setup	Documentation
   DSP Development Kit, Stratix® V Edition	Set the three switches (PCIE_PRSNT2nx1, x4, x8) in dip switch SW6 to ON. This setting selects 8-lane PCIe (default board setting).	https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/v-gs.html
   Cyclone® V GT FPGA Development Kit	Set the two switches(PCIe_x1, x4) in dip switch SW3 to ON. This setting selects 4-lane PCIe (default board setting).	https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-gt.html
   Kintex®-7 KC705	Set jumper J32 so that it connects pins 5 and 6. This setting selects 8-lane PCIe (default board setting).	https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html
   Virtex®-7 VC707	Set jumper J49 so that it connects pins 5 and 6. This setting selects 8-lane PCIe (not the default board setting).	https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html

3. Turn off the host computer.

4. Install the FPGA development board in a PCI Express slot inside host computer.

5. For AMD boards, plug the external power supply into the wall outlet. Then plug the power supply adapter cable into the FPGA development board.

   Intel^® boards do not use an external power supply.

6. Connect the JTAG cable to the FPGA development board and the computer. When you use PCI Express for FIL simulation, the JTAG cable is still required to program the FPGA.

7. Turn on the power switch on the FPGA board.

8. Start up the host computer.

Step 2. Set Up Board Connection

HDL Verifier™ assumes that there is only one download cable connected to the host computer, and that the FPGA programming software can automatically detect this connection. If not, use FPGA programming software to program your FPGA with the correct options.

• JTAG Connection

• Ethernet Connection

• PCI Express Connection

JTAG Connection

  Intel

1. Install USB Blaster I or II cable driver.

2. When using Linux^® operating systems: The Quartus^® II library must be present in LD_LIBRARY_PATH before you start MATLAB. Prepend the Linux distribution library path before the Quartus II library on LD_LIBRARY_PATH. For example, /lib/x86_64-linux-gnu:$QUARTUS_LATEST/../linux64.

 AMD

1. For Linux operating systems: Install Digilent^® Adept2.

Ethernet Connection

Follow these instructions to set up a Gigabit Ethernet network adapter on your computer for FIL simulation.

 Windows 7 Setup

1. Open the Control Panel and type "view network connections" in the search bar. Select View network connections in the search results.

2. Right-click the connection icon to your FPGA development board, and select Properties from the pop-up menu.

   

3. Under This connection uses the following items, select Internet Protocol Version 4 (TCP/IPv4), and click Properties.

   

4. Select Use the following IP address and set IP address to 192.168.0.1. If this address is in use by another computer on your network, change it to any available IP address on this subnet, such as 192.168.0.100. This value indicates your host computer address. Set the Subnet mask to 255.255.255.0.

   The figure shows an example TCP/IP configuration.

   

5. Click OK to exit TCP/IP Properties.

6. Click Close to exit Local Area Connection Properties.

 Windows Vista Setup

1. Open the Control Panel.

2. Click Network and Sharing Center, and then click Manage network connections.

3. Right-click the connection icon to your FPGA development board, and select Properties from the pop-up menu.

4. Under This connection uses the following items, select Internet Protocol Version 4 (TCP/IPv4), and click Properties.

5. Select Use the following IP address and set IP address to 192.168.0.1. If this address is in use by another computer on your network, change it to any available IP address on this subnet, such as 192.168.0.100. This value indicates your host computer address. Set the Subnet mask to 255.255.255.0.

6. Click OK to exit TCP/IP Properties.

7. Click Close to exit Local Area Connection Properties.

 Windows XP Setup

1. Open the Control Panel.

2. Open Network connections.

3. Right-click the connection icon to your FPGA development board, and select Properties from the pop-up menu.

4. Under This connection uses the following items, select Internet Protocol (TCP/IP), and click Properties.

5. Select Use the following IP address and set IP address to 192.168.0.1. If this address is in use by another computer on your network, change it to any available IP address on this subnet, such as 192.168.0.100. This value indicates your host computer address. Set the Subnet mask to 255.255.255.0.

6. Click OK to exit TCP/IP Properties.

7. Click Close to exit Local Area Connection Properties.

 Linux Setup

Use the ifconfig command to set up your local address. For example:

% ifconfig eth1 192.168.0.1

In this example, eth1 is the second Ethernet adapter on the Linux computer. Check your system to determine which Ethernet adapter is connected to the FPGA development board. This command sets the local IP address to 192.168.0.1. If this address is in use by another computer on your network, change it to any available IP address on this subnet, such as 192.168.0.100.

PCI Express Connection

FIL over PCI Express connection is supported only for 64-bit Windows^® operating systems.

1. Install the PCI Express drivers for your board using the FPGA board support package installer.

2. After you program your FPGA development board, restart your computer. The operating system automatically detects the new PCI Express connection. See "Step 9: Integrate and Simulate" > "Load Programming File onto FPGA" > "PCI Express Connection" under Block Generation with the FIL Wizard or System Object Generation with the FIL Wizard.