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GDDR6 x32 Architectural Kit

Implement a 32-bit GDDR6 interface for pre-layout analysis or post-layout verification.

GDDR6 (double data rate type six) SGRAM (synchronous graphics random access memory) is a high bandwidth interface designed for use in graphics cards, game consoles and high-performance computing. GDDR6 interfaces are capable of speeds up to 16 Gb/s.

This GDDR6 architectural signal integrity kit includes all the transfer nets, waveform processing levels, generic timing and simulation models for a GDDR6 interface. This includes generic buffer models for the GDDR6 controller and SGRAM, along with functional timing models and complete waveform processing levels, all of which are easily customizable.

You can modify the kit to match your exact DDR6 implementation. Then, perform complete pre-layout solution space analysis and/or full post-layout verification for waveform quality and timing margins.

Open GDDR6 x32 Kit

Open the GDDR6 x32 kit in the Parallel Link Designer app using the openSignalIntegrityKit function.

openSignalIntegrityKit("GDDR6_x32");

Kit Overview

  • Project name: GDDR6_x32

  • Interface name: x32_gddr6

  • Target data rate: 4 Gb/s (UI = 250 ps)

  • 40 data bits per channel (32 data, 4 DBI and 4 EDC)

  • 1.25V or 1.35V signaling selectable

This kit supports both HSPICE and IsSpice4 simulators. No specific version of either simulator is required when running this kit.

For more information about the generic GDDR6 x32 implementation signal integrity kit, including block diagrams, system configurations, transfer nets and libraries, refer to the document GDDR6_x32.pdf that is attached to this example as a supporting file.

References

[1] Graphics Double Data Rate 6 (GDDR6) SGRAM Standard." JEDEC. JESD250C. February 2021. https://www.jedec.org/standards-documents/docs/jesd250c.

See Also