If you have a subsystem or a Stateflow® chart that does not achieve 100% coverage, and you do not want to convert the subsystem or chart to a Model block, follow this example to achieve full coverage.
The example uses a closed-loop controller model. A closed-loop controller passes instructions to the controlled system and receives information from the environment as the control instructions are executed. The controller can adapt and change its instructions as it receives this information.
sldvdemo_autotrans model is a closed-loop
simulation model. The ShiftLogic Stateflow chart represents the
controller part of this model. Test cases designed in the ManeuversGUI Signal
Builder block drive the closed-loop simulation.
To simulate the model, recording condition, decision, and MCDC coverage for the ShiftLogic controller:
Open the example model:
On the Apps tab, click the arrow on the right of the Apps section.
Under Model Verification, Validation, and Test, click Coverage Analyzer.
On the Coverage tab, click Settings.
On the Coverage pane in the Configuration Parameters dialog box. set the following options:
Select Enable coverage analysis.
Select Subsystem and click Select Subsystem.
In the Subsystem Selection dialog box, select
Under Coverage metrics, select
Condition Decision Coverage (MCDC).
Clear the Other metrics if they are selected.
In the Coverage > Results pane of the Configuration Parameters dialog box, set the following options:
In the cvdata object name field,
covdata_original_controller to specify a
unique name for the coverage data workspace variable.
Select Generate report automatically after analysis.
Start the simulation of the
to record the coverage data.
After the simulation, the coverage report opens. The report indicates that the following coverage is achieved for the ShiftLogic Stateflow chart:
Decision: 87% (27/31)
Condition: 67% (8/12)
MCDC: 33% (2/6) conditions reversed the outcome
The simulation saves the coverage data in the MATLAB® workspace
that contains the coverage data.
Save the coverage data in a file on the MATLAB path:
To find the missing coverage for the ShiftLogic chart, run a subsystem analysis on that block. Use this technique to focus your analysis on an individual part of the model.
To achieve 100% coverage for the ShiftLogic controller, run a test-generation analysis that uses the existing coverage data.
Right-click the ShiftLogic block and select Design Verifier > Options.
In the Configuration Parameters dialog box, under
the Select tree, choose the Design
Verifier node. Under Analysis options in
the Mode field, select
Under the Design Verifier node, select Test Generation. Under Existing coverage data, select Ignore objectives satisfied in existing coverage data.
In the Coverage data file field, enter the name of the file containing the coverage data that you recorded during simulation:
Click Apply to save these settings.
Under the Select tree, click Design Verifier.
On the main Design Verifier pane, click Generate Tests.
The analysis extracts the Stateflow chart into a new model named
The analysis analyzes the new model, ignoring the coverage objectives
previously satisfied and recorded in the
When the test-generation analysis is complete, in the Simulink® Design Verifier™ log window, select Simulate tests and produce a model coverage report.
The report indicates that the following coverage is achieved for the ShiftLogic chart in simulation with the test cases generated by Simulink Design Verifier:
Decision: 84% (26/31)
Condition: 83% (10/12)
MCDC: 67% (4/6) conditions reversed the outcome
Design Verifier report lists six test cases
for the extracted model that satisfy the objectives not covered in
Design Verifier report indicates that two coverage
objectives in the Stateflow chart ShiftLogic are proven unsatisfiable.
The implicit event
tick is never
the ShiftLogic chart is updated at every time step. The analysis cannot
satisfy condition or MCDC coverage for either instance of the temporal
after(TWAIT, tick) is semantically equivalent
Event == tick && temporalCount(tick) >= TWAIT
If you move
after(TWAIT, tick) into the condition,
[after(TWAIT, tick) && speed < down_th]
Design Verifier determines that
so it only tests the
temporalCount(tick) >= TWAIT part
after(TWAIT, tick). The analysis is able to
find test objectives that satisfy condition and MCDC coverage for