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FPGA design (mem channels)

Interconnect clock frequency (MHz)

Frequency of the master datapath to the interconnect controller in MHz.


Default: 200

Interconnect data width (bits)

Data width of master datapath to interconnect controller in bits.


Default: 64

Interconnect FIFO depth (num bursts)

Specify depth of data FIFO, in units of bursts. When the writer has no buffers to write to, the FIFO can absorb data until a buffer becomes available. This value is the maximum number of bursts that can be buffered before data gets dropped.


Default: 12

Interconnect almost-full depth

Specify a number that asserts a backpressure signal from the channel to the data source. To avoid dropping data, set a high watermark, allowing the data producer enough time to react to backpressure. This number must be smaller than the FIFO depth.


Default: 8