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System on Chip (SoC)

Combine processor software, programmable logic, memory, and peripherals into complete SoC designs

Create SoC, MCU, or application-specific SoC Simulink® models of an application. Use preconfigured model templates or follow the SoC model guidelines. SoC Blockset™ model templates provide design patterns and implement best practices for creating an SoC model. The suggested workflow shows the process to combine processor software, user-specified programmable logic, shared memory systems, and on-chip peripherals to create an SoC model of an application. Use analysis functions and tools to estimate the resources that application uses. Compare different architectures to understand design tradeoffs in partitioning between processor software and programmable logic.

The blockset exports reference designs for SoCs, MCUs, ASICs, and FPGAs using Xilinx®, Intel®, and Texas Instruments® design tools. Automatically generate hardware and software code, and then execute the application on an SoC device by using the SoC Builder tool. Code generation requires the HDL Coder™ product, Embedded Coder® product, or both.


Embedded Linux ExplorerConnect to hardware, monitor resources, and control applications running embedded Linux (Since R2023a)


SoC BuilderBuild, load, and execute SoC model on SoC, FPGA, and MCU boards
HDL IP ImporterImport HDL IP core into SoC model (Since R2023a)


socModelAnalyzerEstimate number of operations in Simulink model (Since R2020a)
socFunctionAnalyzerEstimate number of operations in MATLAB function (Since R2020a)
socAlgorithmAnalyzerReportOpen algorithm analysis report (Since R2020a)
socExportReferenceDesignExport custom reference design for HDL Workflow Advisor (Since R2020a)
socTaskSchedulabilityDetermine whether set of tasks can be scheduled for specified core assignments (Since R2022b)
socCreateModelCreates a skeleton SoC Blockset model for task set (Since R2022b)


socModelBuilderBuild, load, and execute SoC model on SoC and FPGA boards (Since R2023a)


Processor, Programmable Logic, and Memory

Application-Specific SoCs

Architecture and Analysis


Build Error When FPGA or Processor Model Not Detected

Unsupported mode in when generating SoC design using SoC Builder.

Build Error for Rapid Accelerator Mode

Unsupported simulation mode in SoC Blockset models and projects.