soc.sdk.ProcessingSystem Class
Namespace: soc.sdk
Processing system definition in FPGACore
object
Description
Use the soc.sdk.ProcessingSystem
class to define the properties of a
processing system in an FPGA core in a soc.sdk.Hardware
object.
Creation
Description
creates an object that represents a processing system interface.processingSystemObj
= soc.sdk.ProcessingSystem(name
)
Properties
Full path to the processing system TCL
file, specified as a
character vector.
Example: '$(TARGET_ROOT)/tcl/ZCU106PS.tcl'
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: char
Full path to constraint file, specified as a character vector.
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: char
Master interface port label, specified as a character vector.
Example: 'zynq_ultra_ps/M_AXI_HPM0_FPD'
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: char
Master interface clock port label, specified as a character vector.
Example: 'zynq_ultra_ps/maxihpm0_fpd_aclk'
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: char
Master interface reset port label, specified as a character vector.
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: char
Slave interface port label, specified as a character vector.
Example: 'zynq_ultra_ps/S_AXI_HPC0_FPD'
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: char
Slave interface clock port label, specified as a character vector.
Example: 'zynq_ultra_ps/saxihpc0_fpd_aclk'
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: char
Slave interface reset port label, specified as a character vector.
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: char
Interrupt interface port label, specified as a character vector.
Example: 'zynq_ultra_ps/pl_ps_irq0'
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: char
Minimum to maximum range of slave interface frequency, specified as a two-element numeric vector.
Example: [1 200]
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: double
Specify first read latency as the number of clock cycles elapsed from the address
phase to the first data transfer for the memory controller transactions, specified as a
vector of the min
and the max
values. The default range is [0 100]
.
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: double
Specify the default value of the first write transfer latency between the
FirstWriteLatencyMinMax
range. When not specified, the default
value is the max
value of the range.
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: double
Specify the last write latency as the number of elapsed clock cycles from the last
data transfer to completion of the transaction, including any turn-around time,
specified as a vector of the min
and the
max
values. The default range is [0
100]
.
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: double
Specify the default value of the last write transfer latency between the
LastWriteLatencyMinMax
range. When not specified, the default
value is the max
value of the range.
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: double
Specify the first read latency as the number of clock cycles elapsed from the
address phase to the first data transfer for the memory controller transactions,
specified as a vector of the min
and the
max
values. The default range is [0
100]
.
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: double
Specify the default value of first read latency between the
FirstReadLatencyMinMax
range. The default value is the
max
value of the range.
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: double
Specify the last read latency range as the number of elapsed clock cycles from the
last data transfer to completion of the transaction, including any turn-around time, as
a vector consisting of the min
and the
max
values. The default range is [0
100]
.
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: double
Specify the default value of last read latency between the
LastReadLatencyMinMax
range. The default value is the
max
value of the range.
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: double
Slave interface data width, specified as a numeric vector.
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: double
Label of the clock output port connected to the FPGA, specified as a character vector.
Example: 'zynq_ultra_ps/pl_clk0'
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: char
Frequency of the clock output port connected to the FPGA, specified as a positive scalar numeric value.
Example: 100
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: double
Label of the reset output port connected to the FPGA, specified as a character vector.
Example: 'zynq_ultra_ps/pl_resetn0'
Attributes:
GetAccess | public |
SetAccess | public |
Data Types: char
Version History
Introduced in R2019b
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