Setup for ARM Targeting with IP Core Generation Workflow

R2026b

The hardware setup tool you use when you install SoC Blockset™ Support Package for AMD FPGA and SoC Devices performs these steps for you. You can also manually call these commands to set up for generating embedded ARM^® code by using the IP core generation workflow.

You must have Embedded Coder^® and SoC Blockset Support Package for AMD FPGA and SoC Devices installed.

1. Register the root directory that is used by the cross-compilation toolchain. This toolchain is used when generating code to target the ARM portion of the Zynq device.

   setupvisionzynqsysroot() 

2. Create a communication link to the Zynq^® board. Use the IP address that you configured for your board. The generated software interface models use this link.

   zynq('Linux','192.168.4.2','root','root','/tmp');