Communication Between Cores Using IPC Blocks

The C2000™ Microcontroller Blockset library provides a set of IPC (Inter-Processor Communication) blocks that facilitate communication between the cores in F2837xD and F2838x processors. These IPC blocks include:

• IPC Receive: Use separate models for each core to receive data from either core.

• IPC Transmit: Transmit data to either core while utilizing separate models for each core.

• Interprocess Data Read: Receive messages from another processor via an Interprocess communication channel.

• Interprocess Data Write: Send messages to another processor using Interprocess Data Write.

To help you choose the right solution for your application, here is a brief comparison between the IPC Transmit/Receive blocks and Interprocess Data Read/Write blocks:

• IPC Transmit/Receive Blocks: These blocks are ideal for scenarios where you need separate models for each core and want to transmit or receive data between them efficiently. They offer core-level control and flexibility.

• Interprocess Data Read/Write Blocks: If you require communication between processors using an Interprocess communication channel, these blocks are the go-to choice. They enable seamless message exchange between processors, making them suitable for inter-processor data sharing.

Selecting the most suitable IPC block for your application depends on your specific requirements. Evaluate your needs based on the following information.

Comparison between IPC Transmit/Receive blocks and Interprocess Data Read/Write blocks

Parameter	IPC Transmit and Receive	Interprocess Data Read and Write
Block parameters
Separate models for each core (flat model approach)	IPC Transmit and Receive blocks can be used for IPC communication between cores by running separate models on each core.	Interprocess Data Read and Write blocks can be used for IPC communication between core by running separate models on each core by deselecting Enable simulation port and without the need of Interprocess Data Channel.
Simulation	Not possible	Possible. Select the parameter Enable simulation port to input the simulation message.
Single model triggering multiple cores using Task Manager (multiprocessor modeling approach)	Not possible	Interprocess Data Read and Write blocks can be used along with Interprocess Data Channel to work on multiprocessor modeling approach.
Interrupts	No parameter setting. IPC interrupts are taken care implicitly. All IPC interrupts supported.	Set Enable interrupt parameter at both Tx and Rx side. IPC4 – IPC7 interrupts between CPU1/CPU2 – CM in F2838x processor family is not supported.
Buffer implementation	Ping pong buffer implemented. No option to configure the buffer from user.	Circular buffer of data type is created at the shared message RAM with options from user to configure the same
Blocking mode	Possible	Not possible
Examples showcasing application of blocks	Inter-Processor Communication Using IPC Blocks	Partition Motor Control for Multiprocessor MCUs