NR LDPC Encoder

Perform LDPC encoding according to 5G NR standard

Since R2020a

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Libraries:
Wireless HDL Toolbox / Error Detection and Correction

Description

The NR LDPC Encoder block implements a low-density parity-check (LDPC) encoder with hardware-friendly control signals. The block accepts data bits, a stream of control signals, a base graph number, and lifting sizes. The block outputs encoded bits, a stream of control signals, lifting sizes, and a signal that indicates when the block is ready to accept new inputs.

The block functionality matches that of the function nrLDPCEncode (5G Toolbox). You can use this block for channel coding of downlink and uplink shared channels and paging channel according to 5G new radio (NR) standard TS 38.212 [1].

The block supports scalar and vector inputs. The block provides an architecture suitable for HDL code generation and hardware deployment. For more information, see Algorithms.

Examples

LDPC Encode and Decode of 5G NR Streaming Data

Simulate NR LDPC Encoder and NR LDPC Decoder blocks and compare their hardware-optimized results with results from 5G Toolbox™ functions.

Open Script

Ports

Input

data — Input data bits

scalar | vector

Input data bits, specified as a scalar or a column vector of size 64.

For more information on how to specify vector input data, see Specifying Vector Input.

Data Types: Boolean

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the input frame

• end — Indicates the end of the input frame

• valid — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: bus

bgn — Base graph number

scalar

Base graph number, specified as a scalar. When this value is 0, the block applies bgn 1. When this value is 1, the block applies bgn 2. For more information about bgn 1 and bgn 2, see section 5.3.2, of TS 38.212 [1].

Data Types: Boolean

liftingSize — Input lifting size

scalar

Input lifting size, specified as a scalar.

For an invalid liftingSize value, the block discards the current frame and waits for the new frame.

For more information about the supported lifting size values, see section 5.3.2, of TS 38.212 [1].

Data Types: uint16

Output

data — Encoded output data bits

scalar | vector

Encoded output data bits, returned as a scalar or a column vector of size 64.

The block outputs data bits in a similar format as the input data bits.

Data Types: Boolean

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the output frame

• end — Indicates the end of the output frame

• valid — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: bus

liftingSize — Output lifting size

scalar

Output lifting size, returned as a scalar.

Data Types: uint16

nextFrame — Ready for new inputs

scalar

The block sets this signal to 1 when the block is ready to accept the start of the next frame. If the block receives an input start signal while nextFrame is 0, the block discards the frame in progress and begins processing the new data.

For more information, see Using the nextFrame Output Signal.

Data Types: Boolean

More About

Specifying Vector Input

Vector input data for the block must be specified as a column vector of size 64. You must provide inputs as an integer number of ceil(liftingSize/64) clock cycles.

The total number of clock cycles that the block requires to receive a frame of data bits for encoding is equal to n x ceil(liftingSize/64), where n is the number of columns in the parity check matrix. n depends on the base graph number, specified by the bgn input port. When the bgn port value is 0, the block sets n to 22. When the bgn port value is 1, the block sets n to 10.

These sections show how the block accepts input data bits based on the liftingSize and bgn port values.

liftingSize input value is less than 64 and bgn value is 0

For a liftingSize input value of 2, the block accepts the first two data input bits in each clock cycle and ignores the remaining 62 elements in that clock cycle. The total number of clock cycles the block requires to receive input data bits is 22.

The D_n elements represent data bits, and the X elements represent ignored values.

Input data bits	Number of Clock Cycles
	1 Clock Cycle	2 Clock Cycles	3 Clock Cycles	4 Clock Cycles	...	21 Clock Cycles	22 Clock Cycles
data[0]	D0	D2	D4	D6	...	...	D42
data[1]	D1	D3	D5	D7	...	...	D43
...	X	X	X	X	X	X	X
...	X	X	X	X	X	X	X
data[63]	X	X	X	X	X	X	X

liftingSize input value is greater than 64 and bgn value is 0

For a liftingSize input value of 104, the block accepts 104 data bits in two clock cycles: 64 data bits in the first clock cycle and 40 data bits in the second clock cycle. The block ignores the remaining 24 elements in the second clock cycle. The total number of clock cycles the block requires to receive input data bits is 44.

The D_n elements represent data bits, and the X elements represent ignored values.

Input data bits	Number of Clock Cycles
	1 Clock Cycle	2 Clock Cycles	3 Clock Cycles	4 Clock Cycles	...	...	43 Clock Cycles	44 Clock Cycles
data[0]	D0	D64	D104	D168	...	...	D2184	D2248
data[1]	D1	D65	D105	D169	...	...	D2185	D2249
	...	...	...		...	...	...	...
...	...	D103	...	D207	...	...	...	D2287
...	...	X	...	X	...	...	...	X
data[63]	D63	X	D167	X	...	...	D2247	X

Algorithms

This figure shows the architecture block diagram of the NR LDPC Encoder block.

The architecture consists of Controller, Check Matrix LUT, Shifter, Memory, Nonnegative Position Selector, and XOR Unit blocks. The Controller block controls the data flow to and from the Memory block and provides control signals to control the functionality of all of these blocks. The Check Matrix LUT block consists of 5G NR LDPC standard [1] parity check matrix values. Based on the bgn and liftingSize input port values, the Check Matrix LUT block provides input to the Shifter block. The Systematic Parity Generator block generates parity bits for the first four rows of the parity check matrix and uses those generated parity bits to calculate the parity bits for the remaining rows of the parity check matrix. The Nonnegative Position Selector block selects the nonnegative positions of the parity check matrix. The XOR Unit block performs the modulo operation by completing the encoding operation.

Latency

The latency of the block varies based on the values of the bgn and liftingSize input ports. Because the latency varies, use the nextFrame control signal to determine when the block is ready for a new input frame.

Scalar Input

This figure shows a sample output of the NR LDPC Encoder block with latency. In this case, the bgn and liftingSize input port values are set to 1 and 384, respectively. The latency of the block is 1,840 clock cycles.

Vector Input

This figure shows a sample output of the NR LDPC Encoder block with latency. In this case, the bgn and liftingSize input port values are set to 0 and 384, respectively. The latency of the block is 1,911 clock cycles.

Performance

The performance of the synthesized HDL code varies with your target and synthesis options.

This table shows the resource and performance data synthesis results. The generated HDL is targeted to the Xilinx^® Zynq^®- 7000 ZC706 evaluation board.

Input Data	Slice LUTs	Slice Registers	Block RAMs	Maximum Frequency in MHz
Scalar	6748	7084	2.5	431
Vector	7951	8504	3.5	430

References

[1] 3GPP TS 38.212. “NR; Multiplexing and Channel Coding.” 3rd Generation Partnership Project; Technical Specification Group Radio Access Network.

[2] Gallager, R. “Low-Density Parity-Check Codes.” IEEE Transactions on Information Theory 8, no. 1 (January 1962): 21–28. www.doi.org/10.1109/TIT.1962.1057683.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Version History

Introduced in R2020a