OFDM Channel Estimator

Estimate channel using input data and reference subcarriers

Since R2020a

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Libraries:
Wireless HDL Toolbox / Modulation

Description

The OFDM Channel Estimator block estimates a channel using input data and reference subcarriers. The block accepts data subcarriers, a valid control port, and refData and refValid reference ports. The block outputs channel estimates and a valid control port. The block allows you to specify the number of subcarriers to estimate for each output symbol.

You can use this block to estimate multipath faded channels on the receiver side in different communications standards, such as long term evolution (LTE) [1] and wireless local area network (WLAN) [4]. To perform proper channel estimation, the refData and refValid ports must be synchronized with the data and valid ports, respectively. For more information about channel estimation and reference data, see Channel Estimation (LTE Toolbox).

This block provides an interface and architecture suitable for HDL code generation and hardware deployment.

Examples

Estimate Channel Using Input Data and Reference Subcarriers

Estimate channel using input data and reference subcarriers.

Open Script

Ports

Input

data — Input data subcarriers

scalar

Input data subcarriers, specified as a scalar of real or complex values.

The software supports double and single data types for simulation, but not for HDL code generation.

Data Types: single | double | int8 | int16 | int32 | signed fixed point
Complex Number Support: Yes

valid — Indicates valid input data

scalar

Indicates valid input data, specified as a scalar.

This port is a control signal that indicates when the sample from the data input port is valid. When this value is 1, the block captures the values from the data input port. When this value is 0, the block ignores the values from the data input port.

Data Types: Boolean

refData — Reference data subcarriers

scalar

Reference data subcarriers, specified as a scalar of real or complex values.

Reference data must be a sequence of unimodular values. In a sequence of values, r₁, r₂, r₃…, r_n, the values are unimodular if r_j x r_j^* = 1,

where:

• j = 1, 2, 3, …, n.

• r_j^* is the complex conjugate of r_j.

Data Types: single | double | int8 | int16 | int32 | signed fixed point
Complex Number Support: Yes

refValid — Indicates valid reference data

scalar

Indicates valid reference data, specified as a scalar.

This port is a control signal that indicates when the sample from the refData input port is valid. When this value is 1, the block captures the values from the refData input port. When this value is 0, the block ignores the values from the refData input port.

refValid port values must be synchronized with valid port values.

Data Types: Boolean

numScPerSym — Number of valid subcarriers per OFDM symbol

scalar

Number of valid subcarriers per OFDM symbol, specified as a scalar in the range from 2 to 65,536.

To support the minimum number of subcarriers per symbol, numScPerSym must be of data type fixdt(0,k,0), where k is greater than or equal to 2.

Dependencies

To enable this port, select the Enable averaging parameter or Enable interpolation parameter.

Data Types: uint8 | uint16 | uint32 | unsigned fixed point

reset — Clear internal states

scalar

Clear internal states, specified as a scalar. When this value is 1, the block stops the current calculation and clears all internal states.

Dependencies

To enable this port, select the Enable reset input port parameter.

Data Types: Boolean

Output

data — Output channel estimates

scalar

Output channel estimates, returned as a scalar. The output data type is the same as the input data.

Data Types: single | double | int8 | int16 | int32 | signed fixed point
Complex Number Support: Yes

valid — Indicates valid output data

scalar

Indicates valid output data, returned as a scalar.

This port is a control signal that indicates when the data output port is valid. The block sets this value to 1 when the data samples are available from the data output port.

Data Types: Boolean

Parameters

Enable averaging — Average LS estimates

off (default) | on

Select this parameter to enable averaging.

Number of symbols to be averaged — Number of symbols to be averaged

2 (default) | integer in range from 2 to 14

Specify the number of symbols to be averaged.

Dependencies

To enable this parameter, select the Enable averaging parameter.

Enable interpolation — Interpolate LS estimates

off (default) | on

Select this parameter to enable interpolation.

Interpolation factor — Interpolation factor

3 (default) | integer in range from 2 to 12

Specify the interpolation factor.

Dependencies

To enable this parameter, select the Enable interpolation parameter.

Maximum number of subcarriers per symbol — Maximum number of subcarriers per symbol

52 (default) | integer in range from 2 to 65, 536

Specify the maximum number of subcarriers per symbol.

Dependencies

To enable this parameter, select the Enable averaging parameter or Enable interpolation parameter.

Enable reset input port — Reset signal

off (default) | on

Select this parameter to enable the reset port on the block icon.

Algorithms

This figure shows the architecture block diagram of the OFDM Channel Estimator block. The block implements least squares (LS) estimation for the channel estimation. To improve the accuracy of LS estimation, the block uses an averaging technique and provides an interpolation feature if the number of known reference signals are limited to certain subcarriers for a particular OFDM symbol. The Least Squares (LS) Estimation block calculates the least-squares estimates using the input data and the reference data.

The Averaging and Interpolation blocks are optional. To perform averaging, select the Enable averaging parameter. To perform interpolation, select the Enable interpolation parameter. The parameters shown in this figure configure the behavior of the block.

The Averaging block accepts the LS estimates and averages the corresponding subcarriers with valid LS estimates over the number of OFDM symbols to be averaged provided in the block mask. This figure shows a sample output of the OFDM Channel Estimator block when only averaging is enabled. In this case, the Number of symbols to be averaged parameter is set to 4, Maximum number of subcarriers per symbol parameter is set to 16, and the numScPerSym port is set to 4.

The block samples the numScPerSym port value at the first valid clock cycle. After that, the block samples this value at the every first valid clock cycle, after completing the valid number of Number of symbols to be averaged x numScPerSym clock cycles. As the number of OFDM symbols to be averaged is 4, the output valid shows the valid channel estimates obtained by averaging over four OFDM symbols.

The Interpolation block accepts the LS estimates and performs linear interpolation to calculate the missing channel information between two consecutive valid LS estimates. This figure shows a sample output of the OFDM Channel Estimator block when only interpolation is enabled. In this case, the Interpolation factor parameter is set to 2, Maximum number of subcarriers per symbol parameter is set to 16, and the numScPerSym port is set to 8.

The block samples the numScPerSym port value at the first valid clock cycle. After that, the block samples this value at the every first valid clock cycle, after completing the valid number of subcarriers per symbol clock cycles. The output valid shows the interpolated LS estimates for two OFDM symbols.

Latency

The latency of the block varies with the block parameter values and numScPerSym port values. This table provides the latency calculations of the block for different conditions.

Enable Averaging Value	Enable Interpolation Value	Latency Value (in Clock Cycles)
Off	Off	12
On	Off	[(Number of symbols to be averaged – 1) x numScPerSym] + 13
Off	On	Interpolation factor + 11
On	On	[(Number of symbols to be averaged – 1) x numScPerSym] + Interpolation factor + 12

This figure shows a sample output of the OFDM Channel Estimator block in an LTE standard configuration. In this case, the Number of symbols to be averaged parameter is set to 14, Interpolation factor parameter is set to 3, Maximum number of subcarriers per symbol parameter is set to 72, and numScPerSym port is set to 72. The latency of the block is 951 clock cycles.

Performance

This table shows the resource and performance data synthesis results of the block when you set the Number of symbols to be averaged parameter to 14, Interpolation factor parameter to 3, Maximum number of subcarriers per symbol parameter to 180, and numScPerSym port to 180. The input data provided is of data type fixdt(1,16,13). The generated HDL is targeted to the Xilinx^® Zynq^®- 7000 ZC706 evaluation board. The design achieves a clock frequency of 244.6 MHz.

Resource	Number Used
Slice LUTs	2684
Slice Registers	1184
DSPs	6
Block RAMs	1.5

References

[1] 3GPP TS 36.211 version 14.2.0 Release 14. "Physical channels and modulation." LTE - Evolved Universal Terrestrial Radio Access (E-UTRA).

[2] Sesia, Stefania, Issam Toufik, and Matthew Baker, eds. LTE - The UMTS Long Term Evolution: From Theory to Practice. Chichester, UK: John Wiley & Sons, Ltd, 2011. https://doi.org/10.1002/9780470978504.

[3] Dahlman, Erik, Stefan Parkvall, and Johan Sköld. 4G LTE/LTE-Advanced for Mobile Broadband. Second edition. Amsterdam ; New York: Elsevier, 2014.

[4] "Wireless LAN Medium Access Control (MAC) and Physical layer (PHY) Specifications." IEEE Std 802.11 – 2012.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Version History

Introduced in R2020a