How to generate VHDL code in Xilinx for discrete PID controller for the controller equation is as u(k)=u(k-1)+(28.2671)e(k)+(-55.5204)e(k-1)+(27.2625)e(k-2) ????
3 visualizaciones (últimos 30 días)
Mostrar comentarios más antiguos
the algorithm is Distributed Arithmetic(DA) algorithm based on LUTs(Look up tables)
0 comentarios
Respuestas (0)
Ver también
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!