Respondida
about the Deep Learning HDL Toolbox Support
You can customize and target the DL HDL Toolbox generated code for any FPGA/ASIC/SoC hardware including Xilinx/AMD devices. h...

alrededor de 2 años hace | 0

Respondida
fimath error in hdl coder
I am assuming you are using MATLAB code to HDL or MATLAB Function Block in Simulink. Can you share your sample model? Usually f...

alrededor de 2 años hace | 0

Respondida
Xilinx ZCU102 not booting with pre-built image
This could be FSBL related error unrelated to HDL Coder. Found several references here. I will try to research a bit more. Pleas...

alrededor de 2 años hace | 0

Respondida
Sending waveform specifications from matlab to fpga
Please reach out to tech support or share a sample testbench (that generates the MRI waveform) and design (intended for FPGA) fo...

alrededor de 2 años hace | 0

Respondida
How to disable clockdriver logic and clr port (automatic added) in generated vhdl code?
This is an integraiton workflow between HDL Coder from MathWorks along with Xilinx System Generator (XSG) from AMD. https://ww...

alrededor de 2 años hace | 0

Respondida
Bug related to using selector block with complex data type in HDL code generation
Can you share your sample model and the release of MATLAB you are encountering this error? Please find the attached model and t...

alrededor de 2 años hace | 0

Respondida
Estimate the resource utilization for custom board that has the Kintex7 chip family
This is a known issue and is being actively resolved. It is due to a bug in the format of the device list for Kintex7 family...

alrededor de 2 años hace | 0

Respondida
HDL code generation for FFT
If you are looking for MATLAB coding style for generating HDL using HDL Coder you can find some samples here. https://www.mat...

alrededor de 2 años hace | 0

Respondida
matlab code for hdl conversion
HDLCoder Design Patterns and Examples This link has several tutorials in this submission show how to generate HDL from MATLAB...

alrededor de 2 años hace | 0

Respondida
Native floating-point latency and adding delay block.
You can just model the math and let HDL Coder figure out how to pipeline the design. >> makehdl('dut_nfp/Su...

alrededor de 2 años hace | 1

Respondida
Failed Internal Error: Could not connect the blocks in the model during HDL Code generation
This usually indicates the model cannot be put in a compiled state prior to HDL Code generation. You should consider restart...

alrededor de 2 años hace | 0

Respondida
How can I connect fpga board basys3ᵀᴹ to Matlab simulink ?
You can use this example as a reference to create a workflow for your Basys Board. https://www.mathworks.com/help/hdlcoder/ug/d...

alrededor de 2 años hace | 0

Respondida
How to implement a digital control transfer function on an FPGA using HDL coder?
Have you considered realizemdl function to generate a Simulink and using HDL Coder to generate code from the Simulink model? ...

alrededor de 2 años hace | 0

Respondida
whether regressionenseblepredict block can be used in hdl coder?
In general the code you posted cannot be directly be used to generate HDL. You need to break the code into design.m (DUT) an...

alrededor de 2 años hace | 0

Respondida
Integrating HDL QPSK Transmitter and Receiver into Xilinx Vivado
HDL QPSK Transmitter and Receiver https://www.mathworks.com/help/comm/ug/hdlqpsktransmitterreceiver.html This example shows ...

alrededor de 2 años hace | 0

Respondida
Does MathWorks support the VC707 with HDL Coder & HDL Verifier? If yes, starting at what version of your tools and ending with what version?
HDL Coder supports several evaluation boards out of the box. Virtex-7 VC707 development board is supported out of the box. http...

alrededor de 2 años hace | 1

| aceptada

Respondida
Training data from a read of the input datastore contains invalid bounding boxes
This example is about yolov2 but may have some useful training and deployment tips. https://www.mathworks.com/help/deep-learn...

más de 2 años hace | 0

| aceptada

Respondida
Unable to update models in OFDMTxVerification.m
I am unable to reproduce the issue. Attaching the generated HDL code. >> license inuse matlab >> runOFDMTransmitterMode...

más de 2 años hace | 0

Respondida
Unable to update models in OFDMTxVerification.m
>> can give any suggestions or references for beginners to use Simulink for HDL synthesis? https://www.mathworks.com/matlabce...

más de 2 años hace | 0

Respondida
How to add TCL script to HDL Coder IP Core generation
In the HDL Workflow Advisor for Generic ASIC/FPGA workflow, in the FPGA Synthesis and Analysis > Create Project task, in the Add...

más de 2 años hace | 0

Respondida
The obtained FPGA (Hardware-in-the-loop) output waveform is inconsistent with Simulink simulation results.
Using Simulink / Simscape for modeling and targeting a State space model to FPGA hardware is well established HDL Coder workflow...

más de 2 años hace | 0

| aceptada

Respondida
HDL Coder to / downto order
The control is now available starting R2023b release for boolean arrays. https://www.mathworks.com/help/releases/R2023b/hdlc...

más de 2 años hace | 0

Respondida
Can I control the HDL to/downto designation used for arrays during HDL generation?
The control is available starting R2023b release for boolean arrays. https://www.mathworks.com/help/releases/R2023b/hdlcoder...

más de 2 años hace | 0

| aceptada

Respondida
HDL-Coder: Vivado gives errors creating bitstream due to disconnected URAM cascade inputs
>> Using Simulink/HDL Coder, I've created a system that works "just great" Glad to hear it. The error you describe in the mess...

más de 2 años hace | 0

Respondida
why matlab throws an error while doing "build model" in soc builder? the error "version 2022.2 of tool xilinx vivado is not supported in hdl workflow advisor. How to fix it?
Each release HDL Coder is tested with specific versions of EDA tools. R2023a release is officially tested with the following v...

más de 2 años hace | 0

Respondida
Represent std_logic_vector in Simulink
HDL Coder supports fixed point data types with integer lengths ranging from 1 to 128 bits. During the HDL code generation proce...

más de 2 años hace | 0

| aceptada

Respondida
matlab function example or suggestion, so that it will generate hdl code in verilog using non blocking assignments
This link has several examples that generate HDL from MATLAB designs. https://www.mathworks.com/matlabcentral/fileexchange/5009...

más de 2 años hace | 0

| aceptada

Respondida
give error in converting the simulation into hdl code
This link provides design patterns of MATLAB Code and Simulink models that let you generate HDL Code. https://www.mathworks.c...

más de 2 años hace | 0

Respondida
HDL Coder can not generate the code
This error is unexpected from HDL Coder that happens when the DUT / referenced model has zero input and output ports. Such subsy...

más de 2 años hace | 0

| aceptada

Respondida
how to generate hdl code for the cyclic prefix removal part of NPARCH fromats using the hdl simulink block set
You need to partition your code into design and testbench files and use MATLAB HDL Coder workflow Try this command to see an ex...

más de 2 años hace | 0

| aceptada