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Comparison 4 numbers without using if action in simulink
https://www.mathworks.com/help/dsp/ref/maximum.html In case you are using Simulink and have access to DSP System Toolbox, max b...

más de 2 años hace | 1

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How to solve this error?
This is an internal and not user facing error. Please reach out to tech support to report the issue and potential workaround.

más de 2 años hace | 1

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hdl generated ip stuck at synthesis part in vivado
Consider using resource report to make sure you are at a high level within the limits of the FPGA resources. sfir_fixed makehd...

más de 2 años hace | 0

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How to initialize DDR External memory, such as InstructionData and WeightData unused dlhdl.Workflow deploy() function
https://www.mathworks.com/help/releases/R2023a/deep-learning-hdl/ug/deploy-simple-adder-network-by-using-MATLAB-deployment-uti...

más de 2 años hace | 0

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Simscape HDL Workflow Simulation Stop Time
Can you share the model if you can that causes the error or reach out to technical support for futher assistance? Thanks

más de 2 años hace | 0

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I'm trying to implement a method used by Mr. Jeff Miller in a Matlab training session entitled "Fixed Point Made Easy," and had a question regarding his use of look-up tables
Can you share the training material and models you are referring to? Looking at the picture you attached the two LUTs are not t...

más de 2 años hace | 0

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Offset binary in Simulink HDL
a = fi(-pi, 1, 6, 0); msb = getmsb(a); c = bitcmp(msb); You can write a MATLAB function block with getmsb and bitcmp functi...

más de 2 años hace | 0

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I have generated HDL IP in matlab but not able to synthesize the IP In Vivado
https://www.mathworks.com/help/hdlcoder/examples.html?category=hdl-code-generation-from-matlab You can check demo examples ...

más de 2 años hace | 1

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CONVOLUTION process with the HDL simulink blocks, does not giving the similar output for the MATLAB script output (highvariations between the simulink and script output))
Caused by: Error using slhdlcoder.SimulinkConnection/initModel Error evaluating parameter 'X' in 'subsystem_simlunik_c...

más de 2 años hace | 0

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Unable to map lookup tables to RAM in HDL coder
Can you share a sample model with your configuration settings and desired synthesis results? All floating point operator level ...

más de 2 años hace | 0

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Kalman filter for FPGA in HDL Coder?
You need to break the MATLAB code into design and testbench and use MATLAB to HDL code advisor. See the sample example below. ...

más de 2 años hace | 0

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Unable to find an installed compiler.
If mex -setup points to a valid compiler; floating point to fixed point conversion should proceed without any errors. if this i...

más de 2 años hace | 0

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Is the creation of a test bench possible, without the use of the HDL coder software?
https://www.mathworks.com/products/matlab-test.html MATLAB Test provides tools for developing, executing, measuring, and managi...

más de 2 años hace | 0

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Do not undertand this error of missing license which contradicts 'license checkout statement'
... so that i can use it to generate HDL code for Microsemi Libero FPGA software ... You can try the examples in this page h...

más de 2 años hace | 0

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Please give latest version numbers of the following modules
Installing MATLAB and typing ver displays the latest version information https://www.mathworks.com/help/matlab/ref/ver.html ve...

más de 2 años hace | 0

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HDL user-defined block RAM
This usually implies generated HDL didn't meet the original MATLAB or Simulink results. Please reach out to technical support ...

más de 2 años hace | 0

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Is it possible to generate a VHDL File from a MATLAB Function that only contains one (clocked) process?
The current code style is driven by synthesis best practices. Please reach to technical support for additional customization r...

más de 2 años hace | 0

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HDL-Coder: initialization of internal VHDL-signals
All HDL Coder generated signals are fully initialized or driven with valid logic. Lack of valid drivers to signals is consid...

más de 2 años hace | 0

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How to create VHDL code of a Neural Network block created through GENSIM command ?
This example shows how to convert a neural network regression model (created using gensim) to HDL Code. https://www.mathworks...

más de 2 años hace | 0

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FPGA Synthesis and Analysis HDL coder
There are many reasons for the synthesis step to be taking a long time. If the generated HDL does not fit on the FPGA or very c...

más de 2 años hace | 0

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how can i use contiuous time integrator in hdl coder?
HDL Coder only generates code from discrete blocks. Continuous blocks are not supported. Consider using discrete time integrat...

más de 2 años hace | 0

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HDL work flow advisor for non evaluation board devices
https://www.mathworks.com/help/hdlcoder/create-a-custom-hardware-platform.html You can create your own custom reference desig...

más de 2 años hace | 0

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Compatibility of HDL coder with regression ensemble predict block and fixed point conversion
RegressionEnsemble Predict' block is currently not supported for HDL code generation. You need to build the block from first pr...

más de 2 años hace | 0

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Add 'MARK_DEBUG = "TRUE"' to signals in generated HDL
Currently synthesis attribute specification is limited to certain blocks like product block. This capability is planned for po...

más de 2 años hace | 0

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Is it possible to generate parametrized HDL for Chart parameters?
https://www.mathworks.com/matlabcentral/answers/382489-how-are-generics-supported-in-hdl-coder Currently type generics are not ...

más de 2 años hace | 0

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The function of generating HDL code has an error with the names of blocks in the same Subsystem
" ... in the subsystem "OFDM Transmitter" will contain the subsystem "whdlOFDMTx Model". When I do generate HDL code, the name o...

más de 2 años hace | 0

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Why I get this error when working with hdl workflow?
This is an unexpected error. Can you reach out to customer support with reproduction steps? Thanks.

más de 2 años hace | 1

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Synthesize Matlab function with large input and output onto FPGA
You have a large IO design (in frames); the design needs conversion to samples. Prior to R2022b release there was no automation ...

más de 2 años hace | 0

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Can't generate Simulink model from Simulink function block
https://www.mathworks.com/help/hdlcoder/ug/hdl-optimizations-across-matlab-function-simulink-blocks.html You can convert a subs...

más de 2 años hace | 0

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How to read a matrix data from a subfunction by HDLs coder
https://www.mathworks.com/matlabcentral/fileexchange/50098-hdlcoder-design-patterns-and-examples HDLCoder Design Patterns and E...

más de 2 años hace | 0