QPSK Transmitter and Receiver in Simulink

This example uses:

This example implements a QPSK transmitter and receiver with Simulink®. The receiver corrects practical wireless communications issues, such as carrier frequency and phase offset, timing drift and frame synchronization. The receiver demodulates the received symbols and outputs a simple message to the Diagnostic Viewer. For a MATLAB® implementation of the same system, refer to the QPSK Transmitter and Receiver example.

Overview

The commqpsktxrx model performs all processing at complex baseband to compensate for a static frequency offset, a timing drift, and Gaussian noise. To cope with these impairments, the model includes a practical digital receiver with correlation-based coarse frequency compensation, PLL-based fine frequency compensation, PLL-based symbol timing recovery, frame synchronization, and phase ambiguity resolution. Blocks available with Communications Toolbox software implement synchronization algorithms in the receiver processing.

Structure of the Example

This figure shows the top-level structure of the model as the transmitter, channel, and receiver subsystems.

The transmitter subsystem consists of:

Bit generation - Generates the bits for each frame
QPSK Modulation - Modulates the bits into QPSK symbols (with Gray mapping)
Transmit filtering - Root raised cosine (RRC) filter with a rolloff factor of 0.5 and upsampling to 2 for the QPSK symbols

The channel subsystem consists of:

AWGN channel with frequency and timing offset impairments - Applies frequency offset, timing drift, and additive white Gaussian noise to the signal

The receiver subsystem consists of:

Automatic gain control (AGC) - Sets the output power level to ensure equivalent gains for the phase and timing error detectors over time
Receive filter - RRC filter with a rolloff factor of 0.5
Coarse frequency compensation - Estimates an approximate frequency offset of the received signal and corrects it
Symbol synchronization - Resamples the input signal according to a recovered timing strobe so that symbol decisions are made at the optimum sampling instants
Carrier synchronization - Compensates for the residual frequency offset and the phase offset
Frame Synchronization - Aligns frame boundaries using the known frame header
Data decoding - Resolves the phase ambiguity caused by the carrier synchronizer, demodulates the signal, and decodes the text message

This section describes and shows detailed structures of the transmitter, channel, and receiver subsystems.

Transmitter

The transmitter includes the Bit Generation subsystem, the QPSK Modulator Baseband block, and the Raised Cosine Transmit Filter block. The Bit Generation subsystem uses a MATLAB workspace variable as the payload of a frame, as shown in the figure below. Each frame contains 20 'Hello world ###' messages and a header. The first 26 bits are header bits, consisting of a 13-bit Barker code repeated two times for the QPSK modulation. Since QPSK symbols contain two bits each, the duplicated Barker code generates precisely 13 QPSK symbols for later use in the Data Decoding subsystem of the receiver model. The remaining bits are the payload which contain the ASCII representation of the message 'Hello world ###', where '###' is a repeating sequence of '000', '001', '002', ..., '099'. The message contains 16 characters and each character is 7 bits. This results in a message length of 16*7=112 bits. The frame payload contains 20 messages, which results in a frame size of 112*20=2240 bits. The Scrambler block ensures a balanced distribution of zeros and ones for the timing recovery operation in the receiver model. The scrambled bits are modulated by the QPSK Modulator Baseband block. The modulated symbols are upsampled by two by the Raised Cosine Transmit Filter block. The symbol rate of the transmitter system is 50k symbols per second, and the sample rate after the Raised Cosine Transmit Filter block is 100k samples per second.

AWGN Channel with Frequency Offset and Variable Delay

The AWGN Channel with Frequency Offset and Variable Delay subsystem first applies the frequency offset and a preset phase offset to the transmit signal. It then adds a variable delay with either ramp or triangle shape to the signal:

Ramp delay - This type of delay is initialized at DelayStart samples, and increases linearly at a rate of DelayStep samples in each frame. When the actual delay reaches one frame, the delay buffer is full, and it maintains a delay of one frame.
Triangle delay - This type of delay linearly changes back and forth between MinDelay samples and MaxDelay samples at a rate of DelayStep samples in each frame.

The use of multiple delay characteristics allows you to investigate their effects on receiver performance, particularly on the ability of Symbol Synchronizer block to compensate for the delay. The delayed signal is processed through an AWGN Channel block.

Receiver

AGC

The received signal amplitude affects the accuracy of the carrier and symbol synchronizer. Therefore, the signal amplitude should be stabilized to ensure an optimum loop design. The AGC output power is set to a value ensuring that the equivalent gains of the phase and timing error detectors stay constant over time. Refer to Chapter 7.2.2 and Chapter 8.4.1 of [ 1 ] for details on how to design the phase detector gain.

Raised Cosine Receive Filter

The receive filter provides matched filtering for the transmitted waveform with a rolloff factor of 0.5. Often the receive filter decimates the input signal by oversample factor to yeild one sample per symbol. However, this model requires an oversampled signal for the subsequent signal recovery operations (timing and frequency recovery). Therefore, the receive filter does not decimate the input signal.

Coarse Frequency Compensation

The Coarse Frequency Compensation subsystem corrects the input signal with a rough estimate of the frequency offset. This figure shows the subsystem that estimates the frequency offset by averaging the output of the correlation-based algorithm of the Coarse Frequency Compensator block. The compensation is performed by the Phase/Frequency Offset block. There is usually a residual frequency offset even after the coarse frequency compensation, which would cause a slow rotation of the constellation. The Carrier Synchronizer block compensates for this residual frequency.

The accuracy of the Coarse Frequency Compensator block decreases with its maximum frequency offset value. Ideally, this value should be set just above the expected frequency offset range. For example, this model introduces a 5 kHz frequency offset and the Coarse Frequency Compensator block has the Maximum frequency offset (Hz) parameter set to 6000.

Symbol Synchronizer

To correct the timing error in the received signal, a Symbol Synchronizer block performs timing recovery with a PLL as described by Chapter 8 of [ 1 ]. The timing error detector is estimated using the rotationally invariant Gardner algorithm. This rotationally invariance of the algorithm means it can be used before or after frequency offset compensation. The input to the block is oversampled by two. On average, the block generates one output symbol for every two input samples. However, when the channel timing error (delay) reaches symbol boundaries, there will be one extra or missing symbol in the output frame. In that case, the block implements bit stuffing/skipping thus the output of this block is a variable-size signal.

The Damping factor, Normalized loop bandwidth , and Detector gain parameters of the block are tunable. Their default values are set to 1 (critical damping), 0.01 and 5.4 respectively, so that the PLL quickly locks to the correct timing while introducing little timing jitter.

Carrier Synchronizer

A Carrier Synchronizer block performs the fine frequency compensation with a phase-locked loop (PLL) implementation that is described by Chapter 7 of [ 1 ]. The fine frequency compensation tracks residual frequency and phase offset in the input signal. The PLL uses a direct digital synthesizer (DDS) to generate the compensating phase that offsets the residual frequency and phase offsets. The DDS estimates the phase offset as the integral of the phase error output of a loop filter.

The Damping factor and Normalized loop bandwidth parameters of the block are tunable. Their default values are set to 1 (critical damping) and 0.01 respectively, so that the PLL quickly locks to the intended phase while introducing little phase noise.

Frame Synchronizer

The frame synchronization is performed by a MATLAB System block using a FrameSynchronizer System object™. The block aligns output to frame boundaries by correlating the known frame header (QPSK-modulated Barker code) against the received QPSK symbols in order to find the location of the frame header. It also transforms the variable-size output of the Symbol Synchronizer block into a fixed-size frame, which is necessary for the downstream processing. The second output of the block is a Boolean scalar used to enable the Data Decoding subsystem to run when a valid frame with the desired header is identified.

Data Decoding

The Data Decoding enabled subsystem performs phase ambiguity resolution, demodulation and text message decoding. Be aware taht the Carrier Synchronizer block may cause a phase ambiguity by locking to the unmodulated carrier with a phase shift of 0, 90, 180, or 270 degrees. For details of phase ambiguity and its resolution, please refer to Chapter 7.2.2 and 7.7 in [ 1 ]. The Phase Offset Estimator subsystem determines this phase shift. The Phase Ambiguity Correction & Demodulation subsystem rotates the input signal by the estimated phase offset and demodulates the corrected data. The payload bits are descrambled, and printed out to the Simulink Diagnostic Viewer at the end of the simulation.

Results and Displays

When you run the simulation, it displays bit error rate and numerous graphical results.

These scopes illustrate the spectrum of the received signal before and after filtering, as well as the signal constellation after filtering, after timing recovery, and after fine frequency compensation.

These constellation diagrams show the output of the Symbol Synchronizer and Carrier Synchronizer blocks respectively.

Exploring the Example

The example allows you to experiment with multiple system capabilities to examine their effect on bit error rate performance. For example, you can view the effect of changing the frequency offset, delay type, and $E_b/N_0$ on the various displays.

This example models a static frequency offset. In practice, the frequency offset might vary over time. This model can still track a time-varying frequency drift via the Coarse Frequency Compensation subsystem. If the actual frequency offset exceeds the maximum frequency offset that can be tracked by the current coarse frequency compensation subsystem, you can increase its tracking range by increasing the oversampling factor. Alternatively, you can change the algorithm from correlation-based to FFT-based, in the Model Parameters block. The FFT-based algorithm performs better than the correlation-based algorithm at low Eb/No.

You can assess the convergence time and estimation accuracy, when you tune the Normalized loop bandwidth and Damping factor parameters of the Symbol Synchronizer and Carrier Synchronizer blocks. In addition, you can assess the pull-in range of the Carrier Synchronizer block. With a large normalized loop bandwidth and damping factor, the PLL can acquire over a greater frequency offset range. However a large normalized loop bandwidth allows more noise, which leads to a large mean squared error in the phase estimation. As noted in [ 1 ], underdamped systems (with damping factor less than one) have a fast settling time, but exhibit overshoot and oscillation and overdamped systems (with damping factor greater than one) have a slow settling time but no oscillations. For more detail on the design of these PLL parameters, you can refer to Appendix C in [ 1 ].

References

1. Michael Rice, "Digital Communications - A Discrete-Time Approach", Prentice Hall, April 2008.