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FFT

Compute fast Fourier transform (FFT)

  • FFT block

Libraries:
DSP HDL Toolbox / Transforms

Description

The FFT block provides two architectures that implement the algorithm for FPGA and ASIC applications. You can select an architecture that optimizes for either throughput or area.

  • Streaming Radix 2^2 — Use this architecture for high-throughput applications. This architecture supports scalar or vector input data. You can achieve gigasamples-per-second (GSPS) throughput using vector input.

  • Burst Radix 2 — Use this architecture for a minimum resource implementation, especially with large fast Fourier transform (FFT) sizes. Your system must be able to tolerate bursty data and higher latency. This architecture supports only scalar input data.

The FFT block accepts real or complex data, provides hardware-friendly control signals, and optional output frame control signals.

Ports

Input

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Input data, specified as a scalar or column vector of real or complex values. Only the Streaming Radix 2^2 architecture supports a vector input. The vector size must be a power of 2, in the range from 1 to 64, and less than or equal to FFT length.

The software supports double and single data types for simulation, but not for HDL code generation.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point
Complex Number Support: Yes

Control signal that indicates if the input data is valid. When valid is 1 (true), the block captures the values from the input data port. When valid is 0 (false), the block ignores the values from the input data port.

Data Types: Boolean

Control signal that clears internal states. When reset is 1 (true), the block stops the current calculation and clears internal states. When the reset is 0 (false) and the input valid is 1 (true), the block captures data for processing.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Dependencies

To enable this port, on the Control Ports tab, select the Enable reset input port parameter.

Data Types: Boolean

Output

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When input is fixed-point data type and scaling is enabled, the output data type is the same as the input data type. When the input is integer type and scaling is enabled, the output is fixed-point type with the same word length as the input integer. The output order is bit-reversed by default. If scaling is disabled, the output word length increases to avoid overflow. Only the Streaming Radix 2^2 architecture supports vector input and output. For more information, see the Divide butterfly outputs by two parameter.

Data Types: double | single | fixed point
Complex Number Support: Yes

Control signal that indicates if the data from the output data port is valid. When valid is 1 (true), the block returns valid data from the output data port. When valid is 0 (false), the values from the output data port are not valid.

Data Types: Boolean

Control signal that indicates that the block is ready for new input data sample on the next cycle. When ready is 1 (true), you can specify the data and valid inputs for the next time step. When ready is 0 (false), the block ignores any input data in the next time step.

For a waveform that shows this protocol, see the third diagram in the Timing Diagram section.

Dependencies

To enable this port, set the Architecture parameter to Burst Radix 2.

Data Types: Boolean

Control signal that indicates the first valid cycle of the output frame. When start is 1 (true), the block returns the first valid sample of the frame on the output data port.

Dependencies

To enable this port, on the Control Ports tab, select the Enable start output port parameter.

Data Types: Boolean

Control signal that indicates the last valid cycle of the output frame. When end is 1 (true), the block returns the last valid sample of the frame on the output data port.

Dependencies

To enable this port, on the Control Ports tab, select the Enable end output port parameter.

Data Types: Boolean

Parameters

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Main

This parameter specifies the number of data points used for one FFT calculation. For HDL code generation, the FFT length must be a power of 2 between 22 to 216.

This parameter specifies the type of architecture.

  • Streaming Radix 2^2 — Select this value to specify low-latency architecture. This architecture type supports GSPS throughput when using vector input.

  • Burst Radix 2 — Select this value to specify minimum resource architecture. This architecture type does not support vector input. When you use this architecture, your input data must comply with the ready backpressure signal.

For more details about these architectures, see Algorithms.

This parameter specifies the complex multiplier type for HDL implementation. Each multiplication is implemented either with Use 4 multipliers and 2 adders or with Use 3 multipliers and 5 adders. The implementation speed depends on the synthesis tool and target device that you use.

This parameter returns output elements in bit-reversed order.

When you select this parameter, the output elements are bit-reversed. To return output elements in linear order, clear this parameter.

The FFT algorithm calculates output in the reverse order to the input. If you specify the output to be in the same order as the input, the algorithm performs an extra reversal operation. For more information, see Linear and Bit-Reversed Output Order.

When you select this parameter, the block expects input data in bit-reversed order. By default, this parameter is disabled, and the block expects the input in linear order.

The FFT algorithm calculates output in the reverse order to the input. If you specify the output to be in the same order as the input, the algorithm performs an extra reversal operation. For more information, see Linear and Bit-Reversed Output Order.

When you select this parameter, the FFT implements an overall 1/N scale factor by dividing the output of each butterfly multiplication by two. This adjustment keeps the output of the FFT in the same amplitude range as its input. If you disable scaling, the FFT avoids overflow by increasing the word length by 1 bit after each butterfly multiplication. The bit increase is the same for both architectures.

Data Types

This parameter specifies the type of rounding mode for internal fixed-point calculations. For more information about rounding modes, see Rounding Modes. When the input is any integer or fixed-point data type, this block uses fixed-point arithmetic for internal calculations. This parameter does not apply when the input data is single or double. Rounding applies to twiddle-factor multiplication and scaling operations.

Control Ports

This parameter enables a reset input port. When you select this parameter, the input reset port appears on the block icon.

This parameter enables a port that indicates the start of output data. When you select this parameter, the output start port appears on the block icon.

This parameter enables a port that indicates the end of output data. When you select this parameter, the output end port appears on the block icon.

Algorithms

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References

[1] Algnabi, Y.S, F.A. Aldaamee, R. Teymourzadeh, M. Othman, and M.S. Islam. “Novel architecture of pipeline Radix 2^2 SDF FFT Based on digit-slicing technique.” 10th IEEE International Conference on Semiconductor Electronics (ICSE). 2012, pp. 470–474.

Extended Capabilities

Version History

Introduced in R2014a

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See Also

Blocks

Objects