setTriggerCombinationOperator

R2026b

Configure operator that combines individual signal value comparisons into overall trigger condition

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Syntax

setTriggerCombinationOperator(DC,operator)
setTriggerCombinationOperator(DC,operator,N)

Description

Add-On Required: This feature requires the HDL Coder Support Package for Intel FPGA and SoC Devices add-on.

setTriggerCombinationOperator(DC,operator) configures the logical operator that combines comparisons of individual signals into an overall trigger condition in trigger stage 1. DC is a customized data capture object.

setTriggerCombinationOperator(DC,operator,N) configures the logical operator that combines comparisons of individual signals into an overall trigger condition in a trigger stage specified by N. DC is a customized data capture object.

Input Arguments

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Customized data capture object, specified as an hdlverifier.FPGADataReader System object.

Logical operator to combine comparisons of individual signals into a trigger condition, specified as AND or OR. The trigger condition comprises value comparisons of one or more signals. To combine value comparisons, you can use only one type of logical operator. For example, suppose three signals, A, B, and C, make up the trigger condition. The options are:

  • A == 10 AND B == 'Falling edge' AND C == 0
  • A == 10 OR B == 'Falling edge' OR C == 0

You cannot mix and match the combination operators. For details on trigger conditions, see Triggers.

Trigger stage, specified as an integer from 1 to M, where M is set by the Max trigger stages parameter of the FPGA Data Capture Component Generator tool. Use N to set the combination operator in Nth trigger stage. If you do not specify N, by default, the function sets the combination operator in trigger stage 1.

Version History

Introduced in R2017a

See Also

Objects

Tools