Model Configuration Parameters: Global Settings

The Global Settings category enables you to specify detailed characteristics of the generated code, such as HDL element naming, coding style, whether you want the HDL code to conform to coding standards, and diagnostics and additional options for model generation and HDL code generation.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings category.

Parameter	Description
Reset type	Asynchronous or synchronous reset logic for registers.
Reset asserted level	Asserted or active level of the reset input signal.
Clock input port	Name for clock input port.
Clock enable input port	Name for clock enable input port.
Reset input port	Name for reset input port.
Clock inputs	Generation of single or multiple clock inputs.
Treat Simulink rates as actual hardware rates	Oversampling value based on model rates.
Clock edge	Active clock edge.
Oversampling factor	Oversampling value.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > General category.

Parameter	Description
Verilog file extension	File name extension for generated Verilog^® files.
VHDL file extension	File name extension for generated VHDL^® files.
SystemVerilog file extension	File name extension for generated SystemVerilog files.
Package postfix	Text to append to model or subsystem name.
Entity conflict postfix	Text to resolve duplicate module names.
Split entity file postfix	Text to be appended to model name to form name of generated entity file.
Reserved word postfix	Text to append to value names, postfix values, or labels.
Split arch file postfix	Text to be appended to model name to form name of generated architecture file.
Clocked process postfix	Postfix as character vector.
Split entity and architecture	Number of files entity and architecture code is written to
Complex real part postfix	Text to append to real part of complex signal names.
VHDL architecture name	Architecture name for DUT.
Complex imaginary part postfix	Text to append to imaginary part of complex signal names.
Module name prefix	Prefix for module or entity name.
Enable prefix	Base name as character vector.
Timing controller postfix	Postfix as character vector.
Pipeline postfix	Text to append to names of input or output pipeline registers.
VHDL library name	Target library name for generated VHDL code.
Generate VHDL or SystemVerilog code for model references into a single library	Code placement for model references.
Block generate label	Postfix to block labels used for HDL `GENERATE` statements.
Output generate label	Postfix to output assignment block labels.
Instance generate label	Text to append to instance section labels.
Vector prefix	Prefix to vector names.
Instance prefix	Prefix to generated component instance names.
Instance postfix	Postfix to generated component instance names.
Map file postfix	Postfix appended to file name for generated mapping file.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > Ports category.

Parameter	Description
Input data type	HDL data type for the input ports of the model.
Output data type	HDL data type for the output ports of the model.
Clock enable output port	Name for the generated clock enable output port.
Minimize clock enables	Minimize clock enable logic.
Minimize global resets	Minimize reset logic.
Use trigger signal as clock	Trigger input signal.
Enable HDL DUT input port generation for tunable parameters	Enable creation of DUT input ports for tunable parameters.
Balance delays for generated DUT input ports	Insert matching delays on generated DUT inport port paths.
Enable HDL DUT output port generation for test points	Enable creation of DUT output ports for the test point signals.
Balance delays for generated DUT output ports	Insert matching delays on generated DUT output port paths.
Scalarize ports	Vector ports flattened into scalar ports.
Max number of I/O pins for FPGA deployment	Maximum number of I/O pins for target FPGA.
Check for DUT pin count exceeding I/O Threshold	Message generated when DUT pin count exceeds maximum number of I/O pins.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > Coding style category.

Parameter	Description
Represent constant values by aggregates	Constants represented by aggregates.
Inline MATLAB Function block code	Inline HDL code for MATLAB Function blocks.
Initialize all RAM blocks	Generate initial signal value for RAM blocks.
RAM Architecture	RAM architecture with or without clock enable.
No-reset registers initialization	Initialize registers without reset and mode of initialization.
Minimize intermediate signals	Optimize HDL code for debuggability or code coverage.
Unroll For-Generate Loops	Unroll and omit `FOR` and `GENERATE` loops from generated HDL code.
Generate parameterized HDL code from masked subsystem	Generate reusable HDL code for subsystems.
Enumerated Type Encoding Scheme	Encoding scheme represent enumeration types.
Use “rising_edge/falling_edge” style for registers	Specify if generated should code use `rising_edge` function or `falling_edge` function.
Code reuse	Single reusable file to represent the subsystem logic.
Inline VHDL configuration	Specify if generated VHDL code includes inline configurations.
Concatenate type safe zeros	Syntax for concatenated zeros in generated VHDL code.
Generate obfuscated HDL code	Specify generation of obfuscated HDL code.
Preserve Bus structure in the generated HDL code	Generate code with VHDL record or SystemVerilog structure types.
Indexing for scalarized port naming	Starting index for the names of scalarized vector ports.
Optimize timing controller	Timing controller entity for speed and code size.
Timing controller architecture	Architecture of generated timing controller.
Use Verilog or SystemVerilog `timescale directives	Use of compiler directives in generated Verilog or SystemVerilog code.
Verilog or SystemVerilog timescale specification	Timescale to use in generated Verilog or SystemVerilog code.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > Coding standards category.

Parameter	Description
HDL coding standard	Enable the Industry coding standard guidelines.
Show passing rules in coding standard report	Filter the coding standard report so passing rules do not appear.
Check for duplicate names	Check for duplicate names in the design.
Check for HDL keywords in design names	Check for HDL keywords in design names.
Check module, instance, entity name length	Specify whether to check module, instance, and entity name length.
Check signal, port, and parameter name length	Specify whether to check signal, port, and parameter name length.
Check for clock enable signals	Specify whether to check for clock enable signals in the generated code.
Detect usage of reset signals	Specify whether to check for reset signals in the generated code.
Detect usage of asynchronous reset signals	Specify whether to check for asynchronous reset signals in the generated code.
Minimize use of variables	Specify whether to minimize use of variables.
Check for initial statements that set RAM initial values	Specify whether to check for initial statements that set RAM initial values.
Check for conditional statements in processes	Specify whether to check for length of conditional statements.
Check for assignments to the same variable in multiple cascaded control regions	Specify whether to check if there are assignments to same variable in multiple cascaded control regions.
Check if-else statement chain length	Specify whether to check if-else statement chain length.
Check if-else statement nesting depth	Specify whether to check if-else statement nesting depth.
Check multiplier width	Specify whether to check multiplier bit width.
Check for non-integer constants	Specify whether to check for non-integer constants.
Check line wrap length	Specify whether to check line lengths in the generated HDL code.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > Comments category.

Parameter	Description
Enable Comments	Enable or disable comments.
Comment in header	Comment lines in header of generated HDL and test bench files.
Emit time/date stamp in header	Time and date information in the generated HDL file header.
Include requirements in block comments	Generation of requirements comments.
Custom File Header Comment	Custom file header comment.
Custom File Footer Comment	Custom file footer comment.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > Model Generation category.

Parameter	Description
Generated model	Enable or disable generation of generated model.
Validation model	Enable or disable generation of a validation model.
Prefix for generated model name	Prefix of the generated model name.
Suffix for validation model name	Suffix of the validation model name.
Layout style	Layout style of the generated HDL model.
Auto signal routing	Automatic routing of signals in the generated model.
Inter-block horizontal scaling	Horizontal scaling of generated model.
Inter-block vertical scaling	Vertical scaling of generated model.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > Advanced category.

Parameter	Description
Check for name conflicts in black box interfaces	Specify whether to check for duplicate module or entity names.
Check for presence of reals in generated HDL code	Specify whether to check for reals in the generated HDL code.
Generate HDL code	Enable or disable HDL code generation for model or Subsystem.
Suppress out of bounds access errors by generating simulation-only index checks	Logic that runs during simulation time to prevent array indices from going out of bounds.

The Configuration Parameters dialog box also includes other code generation parameters: