Main Content

addClockInterface

Class: hdlcoder.ReferenceDesign
Package: hdlcoder

Add clock and reset interface

Syntax

addClockInterface('ClockConnection',clock_port,'ResetConnection',reset_port)
addClockInterface('ClockConnection',clock_port,'ResetConnection',reset_port,Name,Value)

Description

addClockInterface('ClockConnection',clock_port,'ResetConnection',reset_port) adds a clock and reset interface to an hdlcoder.ReferenceDesign object.

addClockInterface('ClockConnection',clock_port,'ResetConnection',reset_port,Name,Value) adds a clock and reset interface to the hdlcoder.ReferenceDesign object with additional options specified by one or more Name,Value pair arguments. When you specify these arguments, in the HDL Workflow Advisor, HDL Coder™ adds a Set Target Frequency task. To modify the output clock frequency setting in the reference design clock wizard, in this task, specify the Target Frequency (MHz).

Input Arguments

expand all

Reference design port that is connected to the IP core clock port, specified as a character vector.

Example: 'processing_system7_1/FCLK_CLK0'

Reference design port that is connected to the IP core reset port, specified as a character vector.

Example: 'proc_sys_reset/peripheral_aresetn'

Name-Value Pair Arguments

Specify optional comma-separated pairs of Name,Value arguments. Name is the argument name and Value is the corresponding value. Name must appear inside quotes. You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

The default clock frequency in MHz of the clock module IP in the reference design, specified as an integer. When you open the HDL Workflow Advisor, HDL Coder populates this information for Default (MHz) in the Set Target Frequency task.

Example: 'DefaultFrequencyMHz', 50 specifies the default frequency as 50 MHz.

The minimum clock frequency in MHz of the clock module IP in the reference design, specified as an integer.

Example: 'MinFrequencyMHz', 5 specifies the minimum clock frequency as 5 MHz.

The maximum clock frequency in MHz of the clock module IP in the reference design, specified as an integer. In the HDL Workflow Advisor, HDL Coder sets the Frequency Range (MHz) in the Set Target Frequency task based on the MinFrequencyMHz and MaxFrequencyMHz values that you specify.

Example: 'MaxFrequencyMHz', 500 specifies the maximum clock frequency as 500 MHz.

Port number of the clock output from the clock module IP in the reference design, specified as an integer.

Example: 'ClockNumber', 2 specifies to use the second output port in the clock module IP as the clock port.

The name of the clock module IP in the reference design, specified as a character vector.

Example: 'ClockModuleInstance', 'clk_wiz_1' specifies clk_wiz_1 as the name of the clock module IP.

Introduced in R2015a