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addInternalIOInterface

Class: hdlcoder.ReferenceDesign
Package: hdlcoder

Add and define internal IO interface between generated IP core and existing IP cores

Syntax

addInternalIOInterface('InterfaceID',interface_name,'InterfaceType', interface_type,'PortName',port_name,'PortWidth',port_width,'InterfaceConnection',interface_connection)

Description

addInternalIOInterface('InterfaceID',interface_name,'InterfaceType', interface_type,'PortName',port_name,'PortWidth',port_width,'InterfaceConnection',interface_connection) adds and defines an internal IO interface between the generated IP core and other IP cores in the reference design.

In the HDL Workflow Advisor, if you target a custom reference design that has an internal IO interface, you must map a DUT port to the internal IO interface. In the Target Platform Interface Table, you cannot leave the internal IO interface unassigned.

Input Arguments

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Custom internal IO interface name, specified as a character vector. In the HDL Workflow Advisor, when you select the custom reference design, this name appears as an option in the Target Platform Interface Table.

Example: 'MyCustomInternalInterface'

Interface direction relative to the generated IP core, specified as a character vector.

For example, if the interface is an input to the generated IP core, set interface_type to 'IN'.

Name of generated IP core port in the HDL code, specified as a character vector.

Example: 'MyIPCoreInternalIOInterfacePort'

Bit width of generated IP core port, specified as an integer. You can use DUT ports that have flattened word lengths greater than 128 bits. To model DUT ports that have word lengths greater than 128 bits, use vector data types. For example, to model a 512-bit Data port, use a vector port with four 128-bit scalar ports.

Internal IO interface port to connect with generated IP core port, specified as a character vector. The internal IO interface port is an existing port in the reference design. Its port bit width must match port_width.

Different synthesis tools have different formats for the internal IO interface port.

Synthesis ToolFormat Example

Altera® Quartus II

'internal_ip_0.In0'

Xilinx® Vivado®

'internal_ip_0/In0'

Xilinx ISE

'internal_In0'

Example: 'internal_ip_0.In0'

Example: 'internal_ip_0/In0'

Example: 'internal_In0'

Introduced in R2015b