HDL Workflow Configuration Properties

R2026b

Configure HDL code generation and deployment workflows

HDL workflow configuration properties control HDL code generation and deployment workflow options for the hdlcoder.runWorkflow function. By changing property values, you can customize the workflow for Generic ASIC/FPGA, FPGA-in-the-Loop, IP Core Generation, and Simulink Real-Time FPGA I/O.

To refer to a particular object and property, use dot notation:

hWC = hdlcoder.WorkflowConfig(SynthesisTool='Xilinx Vivado',TargetWorkflow='Generic ASIC/FPGA');
hWC.RunTaskGenerateRTLCodeAndTestbench = true;
hWC.GenerateRTLCode = true;

Generic ASIC/FPGA Workflow

ProjectFolder — Folder for generated project files

'' (default) | character vector

Path to the folder where your generated project files are saved, specified as a character vector.

Example: 'project_file_folder'

Objective — Synthesis tool objective

hdlcoder.Objective.None (default) | hdlcoder.Objective.SpeedOptimized | hdlcoder.Objective.AreaOptimized | hdlcoder.Objective.CompileOptimized | hdlcoder.Objective.Routability | hdlcoder.Objective.Fast | hdlcoder.Objective.Advanced | hdlcoder.Objective.Base

High-level synthesis tool objective, specified as one of these values.

hdlcoder.Objective.None (default)	Do not generate additional Tcl commands.
hdlcoder.Objective.SpeedOptimized	Generate synthesis tool Tcl commands to optimize for speed.
hdlcoder.Objective.AreaOptimized	Generate synthesis tool Tcl commands to optimize for area.
hdlcoder.Objective.CompileOptimized	Generate synthesis tool Tcl commands to optimize for compilation time.

If your synthesis tool is AMD^® ISE and your target workflow is Generic ASIC/FPGA, set the Objective property to hdlcoder.Objective.None.

If your synthesis tool is Synplify^® Elite and your target workflow is Generic ASIC/FPGA, set the Objective property to one of the following:

hdlcoder.Objective.Advanced (default)	Generate synthesis tool Tcl commands to maximum optimization for area, power, and speed.
hdlcoder.Objective.Fast	Generate synthesis tool Tcl commands to optimize for speed.
hdlcoder.Objective.Base	Generate synthesis tool Tcl commands to balance optimization for area, power, and speed.
hdlcoder.Objective.Routability	Generate synthesis tool Tcl commands to optimize routing and area.

For the tool-specific Tcl commands that are added to the synthesis project creation Tcl script, see Synthesis Objective to Tcl Command Mapping.

RunTaskGenerateRTLCodeAndTestbench — Enable task to generate code and test bench

true (default) | false

Enable or disable workflow task to generate code and test bench, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

RunTaskVerifyWithHDLCosimulation — Enable task to verify generated code with HDL cosimulation

true (default) | false

Enable or disable task to verify the generated code with HDL cosimulation, specified as a logical. This option takes effect only when GenerateCosimulationModel is true.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Verify with HDL Cosimulation task.

RunTaskCreateProject — Enable task to create synthesis tool project

true (default) | false

Enable or disable task to create a synthesis tool project, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Create Project task.

RunTaskPerformLogicSynthesis — Enable task to launch synthesis tool and run logic synthesis

true (default) | false

Enable or disable task to launch the synthesis tool and run logic synthesis, specified as a logical. This task is available only when your synthesis tool is AMD ISE or Altera^® Quartus^® II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Logic Synthesis task.

RunTaskPerformMapping — Enable task to map synthesized logic to target device

true (default) | false

Enable or disable task to map the synthesized logic to the target device, specified as a logical. This task is available only when your synthesis tool is AMD ISE or Altera Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.

RunTaskPerformPlaceAndRoute — Enable task to run place and route process

true (default) | false

Enable or disable task to run the place and route process, specified as a logical. This task is available only when your synthesis tool is AMD ISE or Altera Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and Route task.

RunTaskRunSynthesis — Enable task to launch AMD Vivado^® and run synthesis

true (default) | false

Enable or disable task to launch AMD Vivado and run synthesis, specified as a logical. This task is available only when your synthesis tool is AMD Vivado.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Run Synthesis task.

RunTaskRunImplementation — Enable task to launch AMD Vivado and run implementation

true (default) | false

Enable or disable task to launch AMD Vivado and run the implementation step, specified as a logical. This task is available only when your synthesis tool is AMD Vivado.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Run Implementation task.

RunTaskAnnotateModelWithSynthesisResult — Enable task to analyze timing information and highlight critical paths

true (default) | false

Enable or disable task to analyze pre- or post-routing timing information and highlight critical paths in your model, specified as a logical. This task is available only when the target workflow is Generic ASIC/FPGA.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.

GenerateRTLCode — Generate HDL code

true (default) | false

Option to generate HDL code in the target language, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

GenerateTestbench — Generate HDL test bench

false (default) | true

Option to generate an HDL test bench in the target language, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

GenerateValidationModel — Generate validation model

false (default) | true

Generate a validation model, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

AdditionalProjectCreationTclFiles — Additional project creation Tcl files to include in your synthesis project

'' (default) | character vector

Additional project creation Tcl files that you want to include in your synthesis project, specified as a character vector.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Create Project task.

Example: 'L:\file1.tcl;L:\file2.tcl;'

SkipPreRouteTimingAnalysis — Skip pre-route timing analysis logical

false (default) | true

Skip pre-route timing analysis, specified as a logical. If your tool does not support early timing estimation, set to true.

When you enable this option, CriticalPathSource is set to 'post-route'

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.

IgnorePlaceAndRouteErrors — Ignore place and route errors

false (default) | true

Ignore place and route errors, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and route task.

CriticalPathSource — Critical path source

'pre-route' (default) | 'post-route'

Critical path source, specified as a character vector.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.

CriticalPathNumber — Number of critical paths to annotate

1 (default) | 2 | 3

Number of critical paths to annotate, specified as a positive integer from 1 to 3.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.

AnnotateModel — Choose the model to annotate

original (default) | generated

Select the model that you want to annotate, specified as a character vector. You can perform the annotation on the original as well as generated model.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.

ShowAllPaths — Show all critical paths

false (default) | true

Show all critical paths, including duplicate paths, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.

ShowDelayData — Annotate cumulative timing delay on each critical path

true (default) | false

Annotate the cumulative timing delay on each critical path, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.

ShowUniquePaths — Show only the first instance of a critical path

false (default) | true

Show only the first instance of a critical path that is duplicated, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.

AllowUnsupportedToolVersion — Allow unsupported synthesis tool version

false (default) | true

Allows you to use an unsupported synthesis tool version in the HDL Workflow Advisor, specified as a logical. You can set this parameter to true if you want to continue creating the project with the unsupported tool version. By default, HDL Coder™ generates an error if an unsupported tool version is detected. If you set this parameter to true, HDL Coder generates a warning instead. When you are using the supported synthesis tool version, this parameter value is ignored. You do not have to specify the parameter value in an HDL workflow script.

In the HDL Workflow Advisor, this option is in the HDL Workflow Advisor > Set Target > Set Target Device and Synthesis Tool task.

ShowEndsOnly — Show only endpoints of each critical path

false (default) | true

Show the endpoints of each critical path, omitting connecting signal lines, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Annotate Model with Synthesis Result task.

FPGA-in-the-Loop

ProjectFolder — Folder for generated project files

'' (default) | character vector

Path to the folder where your generated project files are saved, specified as a character vector.

Example: 'project_file_folder'

RunTaskGenerateRTLCodeAndTestbench — Enable task to generate code and test bench

true (default) | false

Enable or disable workflow task to generate code and test bench, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

RunTaskVerifyWithHDLCosimulation — Enable task to verify generated code with HDL cosimulation

true (default) | false

Enable or disable task to verify the generated code with HDL cosimulation, specified as a logical. This option takes effect only when GenerateCosimulationModel is true.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Verify with HDL Cosimulation task.

RunTaskBuildFPGAInTheLoop — Enable task to generate a model that contains a FIL block and a testbench around the FIL block

true (default) | false

Enable or disable task to generate a model that contains a FIL block and a testbench around the FIL block specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA-in-the-Loop Implementation > Build FPGA-in-the-Loop task.

GenerateRTLCode — Generate HDL code

true (default) | false

Option to generate HDL code in the target language, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

GenerateTestbench — Generate HDL test bench

false (default) | true

Option to generate an HDL test bench in the target language, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

GenerateValidationModel — Generate validation model

false (default) | true

Generate a validation model, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and Testbench task.

IPAddress — IP address of FPGA board

'192.168.0.2' (default) | character vector

IP address of the FPGA board, specified as a character vector. Default address is '192.168.0.2'.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA-in-the-Loop Implementation > Set FPGA-in-the-Loop Options task.

MACAddress — MAC address of FPGA board

'00-0A-35-02-21-8A' (default) | character vector

MAC address of the FPGA board, specified as a character vector, for example '00-0A-35-02-21-8A'. In most cases, you do not have to change the Board MAC address. If you want to connect more than one FPGA board to a single computer, specify a unique MAC address for each additional board.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA-in-the-Loop Implementation > Set FPGA-in-the-Loop Options task.

SourceFiles — Additional HDL source files for verification

'' (default) | character vector

Additional source files for the HDL design that you want to verify on the FPGA board, specified as a character vector.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA-in-the-Loop Implementation > Set FPGA-in-the-Loop Options task.

Connection — Ethernet, JTAG, or USB Ethernet connection

'JTAG' (default) | 'Ethernet' | 'USB Ethernet'

Ethernet, JTAG, or USB Ethernet connection type to the FPGA development board, specified as a character vector.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA-in-the-Loop Implementation > Set FPGA-in-the-Loop Options task.

RunExternalBuild — Run build process externally

true (default) | false

Option to run build process in parallel with MATLAB^®, specified as a logical. If this option is disabled, you cannot use MATLAB until the build is finished.

FreeRunning — Synchronize MATLAB with DUT executing on FPGA

false (default) | true

Option to synchronize MATLAB with the DUT executing on an FPGA, specified as a logical.

• true — Set MATLAB and FPGA synchronization mode to Free-running FPGA. In this mode, the DUT on the FPGA runs asynchronously with MATLAB. The hardware clock runs continuously inside the FPGA itself.

  Note

  • Free-running FIL supports Ethernet and USB Ethernet interfaces only.

  • Free-running FIL works only when you use FIL with a MATLAB System object™. It does not work when you use FIL with a Simulink^® block.

• false — Set MATLAB and FPGA synchronization mode to Lockstep. In this mode, the DUT on the FPGA operates in lockstep with MATLAB. This mode is the default option and it is implicit in FIL simulation.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA-in-the-Loop Implementation > Set FPGA-in-the-Loop Options task.

EnableFILSysObj — Enable FIL System object

false (default) | true

Option to enable the FIL System object, specified as a logical. Enable this option to generate a host interface script, gs_DUTName_interface_fil.m, where DUTName is the name of the DUT.

This script creates a filObj object for interfacing with the FPGA from MATLAB. The interface script contains MATLAB commands that connect to the hardware and program the FPGA, and examples of how to exchange data with your algorithm as it runs on the hardware.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA-in-the-Loop Implementation > Set FPGA-in-the-Loop Options task.

AllowUnsupportedToolVersion — Allow unsupported synthesis tool version

false (default) | true

Allows you to use an unsupported synthesis tool version in the HDL Workflow Advisor, specified as a logical. You can set this parameter to true if you want to continue creating the project with the unsupported tool version. By default, HDL Coder generates an error if an unsupported tool version is detected. If you set this parameter to true, HDL Coder generates a warning instead. When you are using the supported synthesis tool version, this parameter value is ignored. You do not have to specify the parameter value in an HDL workflow script.

In the HDL Workflow Advisor, this option is in the HDL Workflow Advisor > Set Target > Set Target Device and Synthesis Tool task.

IP Core Generation Workflow

ProjectFolder — Folder for generated project files

'' (default) | character vector

Path to the folder where your generated project files are saved, specified as a character vector.

Example: 'project_file_folder'

ReferenceDesignToolVersion — Current reference design tool version

character vector

Current reference design tool version, specified as a character vector, for example '2017.4'. By default, the code generator selects a reference design tool version that is compatible with the current supported tool version. It is change this default reference design tool version, HDL Coder generates an error.

In the HDL Workflow Advisor, this setting is in the HDL Workflow Advisor > Set Target > Set Target Reference Design task.

IgnoreToolVersionMismatch — Ignore mismatch in reference design tool version

false (default) | true

Whether you want the code generator to ignore a mismatch between the reference design tool version and the supported tool version, specified as a logical.By default, if there is a tool version mismatch, HDL Coder generates an error. If you set this option to true, HDL Coder generates a warning instead.

In the HDL Workflow Advisor, this setting is in the HDL Workflow Advisor > Set Target > Set Target Reference Design task.

RunTaskGenerateRTLCodeAndIPCore — Enable task to generate code and IP core

true (default) | false

Enable or disable workflow task to generate code and IP core for embedded system, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and IP Core task.

AllowUnsupportedToolVersion — Allow unsupported synthesis tool version

false (default) | true

Allows you to use an unsupported synthesis tool version in the HDL Workflow Advisor, specified as a logical. You can set this parameter to true if you want to continue creating the project with the unsupported tool version. By default, HDL Coder generates an error if an unsupported tool version is detected. If you set this parameter to true, HDL Coder generates a warning instead. When you are using the supported synthesis tool version, this parameter value is ignored. You do not have to specify the parameter value in an HDL workflow script.

In the HDL Workflow Advisor, this option is in the HDL Workflow Advisor > Set Target > Set Target Device and Synthesis Tool task.

RunTaskCreateProject — Enable task to create embedded system tool project

true (default) | false

Enable or disable workflow task to create an embedded system tool project, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Create Project task.

RunTaskGenerateSoftwareInterface — Enable task to generate software interface

true (default) | false

Enable or disable workflow task to generate a Simulink software interface model with the IP core driver blocks for embedded C code generation, specified as a logical. In this task, you can also verify the IP core functionality and connect to the onboard memory locations by generating a host interface model, host interface script, or both with the AXI Manager driver.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Generate Software Interface task.

GenerateSoftwareInterfaceModel — Generate Simulink software interface model for SoC device

true (default) | false

Specify whether to generate a Simulink software interface model for an SoC device, specified as a logical. The software interface model is your original model with the AXI driver blocks replacing the parts you want to run on hardware. To use this property, you must set the RunTaskGenerateSoftwareInterface task to true. This property is not available for standalone FPGA boards.

After you generate the Simulink software interface model, you can generate C code from it by using Embedded Coder^®. If you do not have the Embedded Coder hardware support package for the target board installed, this property is not available. For example, if the target hardware board is a Zynq^® device, you must have the SoC Blockset™ Support Package for AMD FPGA and SoC Devices installed.

OperatingSystem — Specify target operating system

'Linux' (default) | character vector

Specify the operating system for embedded processor, specified as a character vector. The operating system is board-specific. To use this property, you must set the RunTaskGenerateSoftwareInterface task to true.

HostTargetInterface — Specify target interface

'Ethernet' (default) | 'JTAG AXI Manager (HDL Verifier)' | 'Ethernet AXI Manager (HDL Verifier)'

Specify an interface that communicates between your host machine and the target hardware. Use one of these options.

• 'JTAG AXI Manager (HDL Verifier)' — Use the JTAG interface to access AXI4 and AXI4-Lite registers on the target hardware. To enable this option, set 'HDLVerifierAXI' reference design parameter to 'JTAG' and map each DUT signal that you want to capture to the AXI4 or AXI4-Lite interface.

• 'Ethernet AXI Manager (HDL Verifier)' — Use the Ethernet interface to access AXI4 and AXI4-Lite registers on the target hardware. To enable this option, set 'HDLVerifierAXI' reference design parameter to 'Ethernet' and map each DUT signal that you want to capture to the AXI4 or AXI4-Lite interface.

• 'Ethernet' — Use the Ethernet interface to access the generated IP core deployed on your target hardware. This option is not available for standalone FPGA boards.

To use this property, you must set the RunTaskGenerateSoftwareInterface task to true.

GenerateHostInterfaceModel — Generate host interface model

false (default) | true

Specify whether to generate a host interface model, specified as a logical. The host interface model enables you to write to or read from the memory-mapped locations on the target hardware over a JTAG or Ethernet cable by using the AXI Manager Write and AXI Manager Read blocks. To use this property, you must set the RunTaskGenerateSoftwareInterface task to true.

To enable this property, specify HostTargetInterface as 'JTAG AXI Manager (HDL Verifier)' or 'Ethernet AXI Manager (HDL Verifier)'.

GenerateHostInterfaceScript — Generate host interface script

true (default) | false

Specify whether to generate a host interface script, specified as a logical. The host interface script contains commands that enable you to connect to the target hardware and to write to or read from the generated IP core by using the AXI driver blocks or the AXI Manager. To use this property, you must set the RunTaskGenerateSoftwareInterface task to true.

RunTaskBuildFPGABitstream — Enable task to generate bitstream for embedded system

true (default) | false

Enable or disable workflow task to generate a bitstream for the embedded system, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Build FPGA Bitstream task.

RunTaskProgramTargetDevice — Enable task to program connected target device

false (default) | true

Enable or disable workflow task to program the connected target device, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Program Target Device task.

GenerateIPCoreReport — Generate HTML documentation for the IP core

true (default) | false

Option to generate HTML documentation for the IP core, specified as a logical. For details, see Custom IP Core Report.

Objective — Synthesis tool objective

hdlcoder.Objective.None (default) | hdlcoder.Objective.SpeedOptimized | hdlcoder.Objective.AreaOptimized | hdlcoder.Objective.CompileOptimized

High-level synthesis tool objective, specified as one of these values.

hdlcoder.Objective.None (default)	Do not generate additional Tcl commands.
hdlcoder.Objective.SpeedOptimized	Generate synthesis tool Tcl commands to optimize for speed.
hdlcoder.Objective.AreaOptimized	Generate synthesis tool Tcl commands to optimize for area.
hdlcoder.Objective.CompileOptimized	Generate synthesis tool Tcl commands to optimize for compilation time.

If your synthesis tool is AMD ISE and your target workflow is Generic ASIC/FPGA, set the Objective to hdlcoder.Objective.None.

For the tool-specific Tcl commands that are added to the synthesis project creation Tcl script, see Synthesis Objective to Tcl Command Mapping.

EnableIPCaching — Create IP cache to reduce reference design synthesis time

false (default) | true

Enable or disable IP caching, specified as a logical. When you enable IP caching, the code generator creates an IP cache. The IP Core Generation workflow uses an out-of-context (OOC) workflow. This workflow synthesizes the IP in the reference design out of context from the top-level design. You can reuse this cache in subsequent project runs, which reduces reference design synthesis time. To learn more, see IP Caching for Faster Reference Design Synthesis.

In the HDL Workflow Advisor, you can specify this setting in the Create Project task.

OperatingSystem — Operating system

'' (default) | character vector

Operating system for embedded processor, specified as a character vector. The operating system is board-specific.

AddLinuxDeviceDriver — Add IP core device driver

false (default) | true

Option to insert the IP core node into the operating system device tree on the SD card on your board, specified as a logical. This option also restarts the operating system and adds the IP core driver as a loadable kernel module.

To use this option, your board must be connected.

RunExternalBuild — Run build process externally

true (default) | false

Option to run build process in parallel with MATLAB, specified as a logical. If this option is disabled, you cannot use MATLAB until the build is finished.

EnableDesignCheckpoint — Use routed design checkpoint file

true (default) | false

Option to expedite bitstream build process by using a routed design checkpoint file from a previous build. specified as a logical. If this option is not selected, you cannot use DefaultCheckpointFile.

Example: hWC.EnableDesignCheckPoint = true;

DefaultCheckpointFile — Option to use default or custom routed design checkpoint file

Default (default) | Custom

Option to specify whether to use the default checkpoint file location or use a custom checkpoint file.

Example: hWC.DefaultCheckPointFile = 'Custom'

RoutedDesignCheckpointFilePath — Option to specify file path for routed design checkpoint file

'hdl_prj\checkpoint\system_routed.dcp' (default) | 'C:\example_project\checkpoint\custom_name.dcp'

Option to specify the path to the custom routed design checkpoint file. If DefaultCheckpointFile is set to Default, you cannot specify a custom path.

Example: hWC.RoutedDesignCheckFilePath = 'c:\example_project\checkpoint\example_file.dcp'

MaxNumOfCoresForBuild — Number of threads and jobs for FPGA bitstream build

'synthesis tool default' (default) | positive integer between 4 and 12

Specify the number of threads and jobs that Vivado uses during FPGA synthesis and implementation. If you set this property to 'synthesis tool default', Vivado uses its default threading and job settings. When you specify a value from 4 to 12, HDL Coder configures Vivado threads and jobs based on the selected value and enables out-of-context (OOC) synthesis when supported by the workflow.

In the HDL Workflow Advisor, this property corresponds to the Number of threads and jobs for build setting in the Build FPGA Bitstream task.

Example: hWC.MaxNumOfCoresForBuild = '8';

ReportTimingFailure — Report timing failures as warnings or errors

hdlcoder.ReportTimingFailure.Error (default) | hdlcoder.ReportTimingFailure.Warning

Select whether to report timing failures when generating the FPGA bitstream, specified as one of these values:

hdlcoder.ReportTimingFailure.Error (default)	Report timing failures as errors by default.
hdlcoder.ReportTimingFailure.Warning	Report timing failures as errors instead of warnings. Use this option if you have implemented the custom logic to resolve timing violations in your design.

TclFileForSynthesisBuild — Use custom or default synthesis tool build script

hdlcoder.BuildOption.Default (default) | hdlcoder.BuildOption.Custom

Select whether to use a custom or default synthesis tool build script, specified as one of these values:

hdlcoder.BuildOption.Default (default)	Use the default build script.
hdlcoder.BuildOption.Custom	Use a custom build script instead of the default build script.

CustomBuildTclFile — Custom synthesis tool build script file

'' (default) | character vector

Full path to a custom synthesis tool build Tcl script file, specified as a character vector. The contents of your custom Tcl file are inserted between the Tcl commands that open and close the project. If TclFileForSynthesisBuild is set to hdlcoder.BuildOption.Custom, you must specify a file.

If you want to generate a bitstream, the bitstream generation Tcl command must refer to the top file wrapper name and location either directly or implicitly. For example, this AMD Vivado Tcl command generates a bitstream and implicitly refers to the top file name and location:

launch_runs impl_1 -to_step write_bitstream

Example: 'C:\Temp\work\build.tcl'

Simulink Real-Time FPGA I/O

ProjectFolder — Folder for generated project files

'' (default) | character vector

Path to the folder where your generated project files are saved, specified as a character vector.

Example: 'project_file_folder'

ReferenceDesignToolVersion — Current reference design tool version

character vector

Current reference design tool version, specified as a character vector, for example '2017.4'. By default, the code generator selects a reference design tool version that is compatible with the current supported tool version. It is change this default reference design tool version, HDL Coder generates an error.

In the HDL Workflow Advisor, this setting is in the HDL Workflow Advisor > Set Target > Set Target Reference Design task.

IgnoreToolVersionMismatch — Ignore mismatch in reference design tool version

false (default) | true

Whether you want the code generator to ignore a mismatch between the reference design tool version and the supported tool version, specified as a logical.By default, if there is a tool version mismatch, HDL Coder generates an error. If you set this option to true, HDL Coder generates a warning instead.

In the HDL Workflow Advisor, this setting is in the HDL Workflow Advisor > Set Target > Set Target Reference Design task.

RunTaskGenerateRTLCodeAndIPCore — Enable task to generate code and IP core

true (default) | false

Enable or disable workflow task to generate code and IP core for embedded system, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code and IP Core task.

AllowUnsupportedToolVersion — Allow unsupported synthesis tool version

false (default) | true

Allows you to use an unsupported synthesis tool version in the HDL Workflow Advisor, specified as a logical. You can set this parameter to true if you want to continue creating the project with the unsupported tool version. By default, HDL Coder generates an error if an unsupported tool version is detected. If you set this parameter to true, HDL Coder generates a warning instead. When you are using the supported synthesis tool version, this parameter value is ignored. You do not have to specify the parameter value in an HDL workflow script.

In the HDL Workflow Advisor, this option is in the HDL Workflow Advisor > Set Target > Set Target Device and Synthesis Tool task.

RunTaskGenerateRTLCode — Enable task to generate RTL code and HDL top-level wrapper

true (default) | false

Enable or disable workflow task to generate RTL code and an HDL top-level wrapper, specified as a logical. When enabled, this task also generates a constraint file that contains pin mapping information and clock constraints.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > HDL Code Generation > Generate RTL Code task.

RunTaskCreateProject — Enable task to create embedded system tool project

true (default) | false

Enable or disable workflow task to create an embedded system tool project, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Create Project task.

RunTaskPerformLogicSynthesis — Enable task to launch synthesis tool and run logic synthesis

true (default) | false

Enable or disable task to launch the synthesis tool and run logic synthesis, specified as a logical. This task is available only when your synthesis tool is AMD ISE or Altera Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Logic Synthesis task.

RunTaskPerformMapping — Enable task to map synthesized logic to target device

true (default) | false

Enable or disable task to map the synthesized logic to the target device, specified as a logical. This task is available only when your synthesis tool is AMD ISE or Altera Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.

RunTaskPerformPlaceAndRoute — Enable task to run place and route process

true (default) | false

Enable or disable task to run the place and route process, specified as a logical. This task is available only when your synthesis tool is AMD ISE or Altera Quartus II.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and Route task.

RunTaskGenerateProgrammingFile — Enable task to generate FPGA programming file

true (default) | false

Enable or disable task to generate an FPGA programming file, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Download to Target > Generate Programming File task.

RunTaskGenerateSimulinkRealTimeInterface — Enable task to generate a model that contains an interface subsystem that you can plug into a Simulink Real-Time™ model

true (default) | false

Enable or disable task to generate a Simulink Real-Time model that contains an interface subsystem, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Download to Target > Generate Simulink Real-Time Interface task.

Objective — Synthesis tool objective

hdlcoder.Objective.None (default) | hdlcoder.Objective.SpeedOptimized | hdlcoder.Objective.AreaOptimized | hdlcoder.Objective.CompileOptimized

High-level synthesis tool objective, specified as one of these values.

hdlcoder.Objective.None (default)	Do not generate additional Tcl commands.
hdlcoder.Objective.SpeedOptimized	Generate synthesis tool Tcl commands to optimize for speed.
hdlcoder.Objective.AreaOptimized	Generate synthesis tool Tcl commands to optimize for area.
hdlcoder.Objective.CompileOptimized	Generate synthesis tool Tcl commands to optimize for compilation time.

If your synthesis tool is AMD ISE and your target workflow is Generic ASIC/FPGA, set the Objective to hdlcoder.Objective.None.

For the tool-specific Tcl commands that are added to the synthesis project creation Tcl script, see Synthesis Objective to Tcl Command Mapping.

AdditionalProjectCreationTclFiles — Additional project creation Tcl files to include in your synthesis project

'' (default) | character vector

Additional project creation Tcl files that you want to include in your synthesis project, specified as a character vector.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Create Project task.

Example: 'L:\file1.tcl;L:\file2.tcl;'

SkipPreRouteTimingAnalysis — Skip pre-route timing analysis logical

false (default) | true

Skip pre-route timing analysis, specified as a logical. If your tool does not support early timing estimation, set to true.

When you enable this option, CriticalPathSource is set to 'post-route'

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Mapping task.

IgnorePlaceAndRouteErrors — Ignore place and route errors

false (default) | true

Ignore place and route errors, specified as a logical.

In the HDL Workflow Advisor, this option is part of the HDL Workflow Advisor > FPGA Synthesis and Analysis > Perform Synthesis and P/R > Perform Place and route task.

RunTaskBuildFPGABitstream — Enable task to generate bitstream for embedded system

true (default) | false

Enable or disable workflow task to generate a bitstream for the embedded system, specified as a logical.

In the HDL Workflow Advisor, this task is the HDL Workflow Advisor > Embedded System Integration > Build FPGA Bitstream task.

EnableDesignCheckpoint — Use routed design checkpoint file

true (default) | false

Option to expedite bitstream build process by using a routed design checkpoint file from a previous build. specified as a logical. If this option is not selected, you cannot use DefaultCheckpointFile.

Example: hWC.EnableDesignCheckPoint = true;

DefaultCheckpointFile — Option to use default or custom routed design checkpoint file

Default (default) | Custom

Option to specify whether to use the default checkpoint file location or use a custom checkpoint file.

Example: hWC.DefaultCheckPointFile = 'Custom'

RoutedDesignCheckpointFilePath — Option to specify file path for routed design checkpoint file

'hdl_prj\checkpoint\system_routed.dcp' (default) | 'C:\example_project\checkpoint\custom_name.dcp'

Option to specify the path to the custom routed design checkpoint file. If DefaultCheckpointFile is set to Default, you cannot specify a custom path.

Example: hWC.RoutedDesignCheckFilePath = 'c:\example_project\checkpoint\example_file.dcp'

MaxNumOfCoresForBuild — Number of threads and jobs for FPGA bitstream build

'synthesis tool default' (default) | positive integer between 4 and 12 both included

Specify the number of threads and jobs that Vivado uses during FPGA synthesis and implementation. If you set this property to 'synthesis tool default', Vivado uses its default threading and job settings. When you specify a value from 4 to 12, HDL Coder configures Vivado threads and jobs based on the selected value and enables out-of-context (OOC) synthesis when supported by the workflow.

In the HDL Workflow Advisor, this property corresponds to the Number of threads and jobs for build setting in the Build FPGA Bitstream task.

Example: hWC.MaxNumOfCoresForBuild = '8';

ReportTimingFailure — Report timing failures as warnings or errors

hdlcoder.ReportTimingFailure.Error (default) | hdlcoder.ReportTimingFailure.Warning

Select whether to report timing failures when generating the FPGA bitstream, specified as one of these values:

hdlcoder.ReportTimingFailure.Error (default)	Report timing failures as errors by default.
hdlcoder.ReportTimingFailure.Warning	Report timing failures as errors instead of warnings. Use this option if you have implemented the custom logic to resolve timing violations in your design.

Version History

Introduced in R2015b

R2024b: IPCoreRepository property will be removed

The IPCoreRepository property of the hdlcoder.WorkflowConfig object will be deprecated in a future release. To copy the generated IP core into an IP repository folder, use the copyfile function.